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11-7
11 High-speed Counters
CP2E CPU Unit Software User’s Manual(W614)
11
-1 Over
vie
w
11
11
-1
-
3
Specifications
11-1-3 Specifications
Item
Description
Pulse input method
(Counting mode)
Increment pulse
inputs
Differential phase
inputs (×4)
Up/down pulse
inputs
Pulse + direction
inputs
Input signal
Increment
Phase-A
Up pulse
Pulse
−
Phase-B
Down pulse
Direction
−
Phase-Z
Reset
Reset
Frequency
and number
of high-
speed
counters
E/S
-type
CPU Unit
100 kHz:
2 counters
10 kHz: 4 counters
50 kHz: 1 counter
5 kHz: 1 counter
100 kHz: 1 counter
10 kHz: 1 counter
100 kHz:
2 counters
N14/20 CPU
Unit
100 kHz:
2 counters
10 kHz: 4 counters
50 kHz: 1 counter
5 kHz: 1 counter
100 kHz: 1 counter
10 kHz: 1 counter
100 kHz:
2 counters
N
3
0/40/60
CPU Unit
100 kHz:
3
counters
10 kHz:
3
counters
50 kHz: 2 counters
100 kHz: 2 counters
100 kHz:
2 counters
Counting mode
Linear mode or circular (ring) mode
Count values
Linear mode:
8
000 0000 to 7FFF FFFF hex
Ring Mode: 0000 0000 to Ring SV
High-speed counter PV
storage locations
High-speed counter 0: A271 (upper 4 digits) and A270 (lower 4 digits)
High-speed counter 1: A27
3
(upper 4 digits) and A272 (lower 4 digits)
High-speed counter 2: A
3
17 (upper 4 digits) and A
3
16 (lower 4 digits)
High-speed counter
3
: A
3
19 (upper 4 digits) and A
3
1
8
(lower 4 digits)
High-speed counter 4: A
3
2
3
(upper 4 digits) and A
3
22 (lower 4 digits)
High-speed counter 5: A
3
25 (upper 4 digits) and A
3
24 (lower 4 digits)
The PVs are refreshed in the overseeing processes at the start of each cycle. Use
PRV to read the most recent PVs.
Data format:
8
digit hexadecimal
•
Range in linear mode:
8
000 0000 to 7FFF FFFF hex
•
Range in Ring Mode: 0000 0000 to Ring SV (Circular Max. Count)
Control
method
Target value
comparison
Up to 6 target values and corresponding interrupt task numbers can be registered.
Range
comparison
Up to 6 ranges can be registered, with a separate upper limit, lower limit, and inter-
rupt task number for each range.
Counter reset method
•
Phase-Z + Software reset
The high-speed counter is reset when the phase-Z signal goes ON while the
Reset Bit (A5
3
1.00 to A5
3
1.05) is ON. (Phase Z cannot be used for the incre-
ment pulse.)
•
Software reset
The high-speed counter is reset when the Reset Bit (A5
3
1.00 to A5
3
1.05) is
turned ON.
Operation can be set to stop or continue the comparison operation when the high-
speed counter is reset.
Содержание SYSMAC CP Series
Страница 1: ...USER S MANUAL Cat No W614 E1 01 SYSMAC CP Series CP2E E D CP2E S D CP2E N D CP2E CPU Unit Software ...
Страница 3: ......
Страница 32: ...1 Overview 1 4 CP2E CPU Unit Software User s Manual W614 ...
Страница 44: ...3 CPU Unit Operation 3 8 CP2E CPU Unit Software User s Manual W614 ...
Страница 116: ...6 I O Allocation 6 8 CP2E CPU Unit Software User s Manual W614 ...
Страница 144: ...7 PLC Setup 7 28 CP2E CPU Unit Software User s Manual W614 ...
Страница 170: ...10 Interrupts 10 14 CP2E CPU Unit Software User s Manual W614 ...
Страница 200: ...11 High speed Counters 11 30 CP2E CPU Unit Software User s Manual W614 ...
Страница 272: ...12 Pulse Outputs 12 72 CP2E CPU Unit Software User s Manual W614 ...
Страница 278: ...13 PWM Outputs 13 6 CP2E CPU Unit Software User s Manual W614 ...
Страница 460: ...18 Programming Device Operations 18 28 CP2E CPU Unit Software User s Manual W614 ...
Страница 576: ...Revision 2 CP2E CPU Unit Software User s Manual W614 ...
Страница 577: ......