Renesas SH7041 Series, Hardware Manual, Page: 905 / 923

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Table C.2 Pin Modes During Reset, Power-Down, and Bus Right Release Modes (112 Pin,
120 Pin)
Pin modes
Pin Function Reset Power-Down Bus Right
Standby in Bus
Class Pin Name Power-On Manual Standby Sleep Release Right Release
Clock CK O O H
*
1
O O O
System
RES
I I I I I I
control
MRES
Z
*
4
I Z I I Z
WDTOVF
O
*
3
O
*
3
O O O O
BREQ
Z
*
4
I Z I I I
BACK
Z
*
4
O Z O L L
Interrupt NMI I I I I I I
IRQ0
–
IRQ7
Z
*
4
I Z I I Z
IRQOUT
Z
*
4
O Z H O Z
Address
bus A0–A21 O
*
2
O Z O Z Z
Data bus D0–D31 Z
*
4
I/O Z I/O Z Z
Bus
WAIT
Z
*
4
I Z I Z Z
control
RDWR,
RAS
Z
*
4
O O O Z Z
CASH
,
CASL
Z
*
4
O O O Z Z
RD
H O Z O Z Z
CS0
,
CS1
H O Z O Z Z
CS2
,
CS3
Z
*
4
O Z O Z Z
WRH
,
WRL
H O Z O Z Z
AH
Z
*
4
O Z O Z Z
DMAC DACK0–DACK1 Z
*
4
O Z O O Z
DRAK0–DRAK1 Z
*
4
O Z O O Z
DREQ0
–
DREQ1
Z
*
4
I Z I I Z
MTU TIOC0A–TIOC0D,
TIOC1A–TIOC1D,
TIOC2A–TIOC2D,
TIOC3A, TIOC3C Z
*
4
I/O K
*
1
I/O I/O K
*
1
TIOC3B,TIOC3D,
TIOC4A–TIOC4D Z
*
4
I/O Z I/O I/O Z
TCLKA–TCLKD Z
*
4
I Z I I Z