Renesas SH7041 Series, Hardware Manual, Page: 208 / 923

170
Bit: 15 14 13 12 11 10 9 8
— — MTU
RWE
— — — — IOE
Initial value: 0 0 1 0 0 0 0 0
R/W: R R R/W R R R R R/W
Bit: 7 6 5 4 3 2 1 0
A3LG A2LG A1LG A0LG A3SZ A2SZ A1SZ A0SZ
Initial value: 0 0 0 0 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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Bits 15, 14, 12–9—Reserved: These bits always read as 0. The write value should always be 0.
•
Bit 13—MTU Read/Write Enable (MTURWE): When this bit is 1, MTU control register
access is enabled. See section 12, Multifunction Timer Pulse Unit (MTU), for details.
Bit 13 (MTURWE) Description
0 MTU control register access is disabled
1 MTU control register access is enabled (initial value)
•
Bit 8—Multiplex I/O Enable (IOE): Selects the use of CS3 space as ordinary space or
address/data multiplex I/O space. A 0 selects ordinary space and a 1 selects address/data
multiplex I/O space. When address/data multiplex I/O space is selected, the address and data
are multiplexed and output from the data bus. When CS3 space is an address/data multiplex
I/O space, bus size is decided by the A14 bit (A14 = 0: 8 bit, A14 = 1: 16 bit).
Bit 8 (IOE) Description
0 CS3 space is ordinary space (initial value)
1 CS3 space is address/data multiplex I/O space
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Bit 7—CS3 Space Long Size Specification (A3LG): Specifies the CS3 space bus size. This is
effective only when CS3 space is ordinary space. When CS3 space is an address/data multiplex
I/O space, bus size is decided by the A14 bit.
Bit 7 (A3LG) Description
0 According to the A3SZ bit specified value (initial value)
1 Longword (32 bit) size