Renesas SH7041 Series, Hardware Manual, Page: 441 / 923

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When TCNT3 and TCNT4 count up to H'FFFF, a compare-match occurs with TGR3A, and
TCNT3 and TCNT4 are both cleared. At this point, TSR3’s TCFV bit is not set, but the TCFV bit
of TSR4 is set.
This can be avoided by sync setting for channel 3 and channel 4. Set the SYNC3 and SYNC4 bits
of the timer sync register (TSYR) to 1, compare-match with TGR3A by TCR3 for the counter
clear source, and sync clear with TCR4. This gives the sync setting for channels 3 and 4.
Figure 12.89 shows a TCFV bit operation example in reset sync PWM mode with a set value for
cycle register TGR3A of H'FFFF, when a TGR3A compare-match has been specified without
synchronous setting for the counter clear source.
TGR3A
(H'FFFF)
H'0000
TCF3V
TCF4V
TCNT3 = TCNT4
Counter cleared by compare match A3
Not set
Set
Figure 12.89 Reset Sync PWM Mode Overflow Flag
•
A mask operation
For A mask, the above operation is modified as follows:
When set to reset sync PWM mode, TCNT3 and TCNT4 start counting when the CST3 bit of
TSTR is set to 1. At this point, TCNT4’s count clock source and count edge obey the TCR3
setting.
In reset sync PWM mode, with cycle register TGR3A’s set value at H'FFFF and specifying
TGR3A compare-match for the counter clear source,
the operation of the overflow flag TCFV
bit for both TSR3 and TSR4 will be the same.
When TCNT3 and TCNT4 count up to H'FFFF, a compare-match occurs with TGR3A, and
TCNT3 and TCNT4 are both cleared.
At this point, TCFV bits for TSR3 and TSR4 are not set.
Figure 12.90 shows a TCFV bit operation example in reset sync PWM mode with a set value
for cycle register TGR3A of H'FFFF, when a TGR3A compare-match has been specified
without synchronous setting for the counter clear source.