Renesas SH7041 Series, Hardware Manual, Page: 119 / 923

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Section 4 Clock Pulse Generator (CPG)
4.1 Overview
The SH7040 Series has an on-chip clock pulse generator (CPG) that generates the system clock
(
φ
), as well as the internal clock (
φ
/2 to
φ
/8192). The CPG consists of an oscillator, a PLL, and a
prescaler.
4.1.1 Block Diagram
A block diagram of the clock pulse generator is shown in figure 4.1.
PLLCAP
CK
EXTAL
XTAL
MD2
MD3
Oscillator
PLL circuit
Clock mode
control circuitry
Prescaler
Within the LSI
φ
φ
/2 to
φ
/8192
Figure 4.1 Block Diagram of the Clock Pulse Generator
4.2 Oscillator
Clock pulses can be supplied from a connected crystal resonator or an external clock.
4.2.1 Connecting a Crystal Oscillator
Circuit Configuration: A crystal oscillator can be connected as shown in figure 4.2. Use the
damping resistance (Rd) listed in table 4.1. Use a 4–10 MHz crystal oscillator (consult your dealer
concerning the compatibility of the crystal oscillator and the LSI).