Renesas SH7041 Series, Hardware Manual, Page: 689 / 923

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19.2.3 Port A Data Register L (PADRL)
PADRL is a 16-bit read/write register that stores data for port A. The bits PA15DR–PA0DR
correspond to the PA15/CK–PA0/RXD0 pins. When the pins are used as ordinary outputs, they
will output whatever value is written in the PADRL; when PADRL is read, the register value will
be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status
rather than the register value is read directly when PADRL is read. When a value is written to
PADRL, that value can be written into PADRL, but it will not affect the pin status. Table 19.4
shows the read/write operations of the port A data register.
PADRL is initialized by an external power-on reset. However, PADRL is not initialized for
manual reset, reset by WDT, standby mode, or sleep mode.
Bit: 15 14 13 12 11 10 9 8
PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 19.4 Read/Write Operation of the Port A Data Register (PADR)
PAIOR Pin Status Read Write
0 Ordinary input Pin status Can write to PADR, but it has no effect on pin status
Other function Pin status Can write to PADR, but it has no effect on pin status
1 Ordinary output PADR value Value written is output by pin
Other function PADR value Can write to PADR, but it has no effect on pin status