Renesas SH7041 Series, Hardware Manual, Page: 237 / 923

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10.5 Address/Data Multiplex I/O Space Access
When the BCR1 register IOE bit is set to 1, the D15–D0 pins can be used for multiplexed
address/data I/O for the CS3 space. Consequently, peripheral LSIs requiring address/data
multiplexing can be directly connected to this LSI.
Address/data multiplex I/O space bus width is selected by the A14 bit, and is 8 bit when A14 = 0
and 16 bit when A14 = 1.
10.5.1 Basic Timing
When the IOE bit of the BCR1 is set to 1, CS3 space becomes address/data multiplex I/O space.
When this space is accessed, addresses and data are multiplexed. When the A14 address bit is 0,
the bus size becomes 8 bit and addresses and data are input and output through the D7–D0 pins.
When the A14 address bit is 1, the bus size becomes 16 bit and address output and data I/O occur
through the D15–D0 pins. Access for the address/data multiplex I/O space is controlled by the
AH
,
RD
, and
WRx
signals.
Address/data multiplex I/O space accesses are done after a 3-cycle (fixed) address output, as an
ordinary space type access (figure 10.17).
CK
CS3
AH
RD
Data
WRx
Data
Address
T
a1
T
a2
T
a3
T
a4
T
1
T
2
Read
Write
Address output
Address output Data output
Data input
Figure 10.17 Address/Data Multiplex I/O Space Access Timing (No Waits)