Renesas SH7041 Series, Hardware Manual, Page: 227 / 923

189
10.4 DRAM Access
10.4.1 DRAM Direct Connection
When address space A31–A24 = H'01 has been accessed, the corresponding space becomes a 16-
Mbyte DRAM space, and the DRAM interface function can be used to directly connect the
SH7040 Series to DRAM.
Row address and column address are always multiplexed for DRAM space. The amount of row
address multiplexing can be selected as from 9 to 12 bits by setting the AMX1 and AMX0 bits of
the DCR.
Table 10.5 AMX Bits and Address Multiplex Output
Row Address Column Address
AMX1 AMX0
Shift
Amount Output Pins Output
Address Output
Address Output
Pins
0 0 9 bit A21–A15 A21–A15 A21–A0 A21–A0
A14–A0 A23–A9
0 1 10 bit A21–A14 A21–A14 A21–A0 A21–A0
A13–A0 A23–A10
1 0 11 bit A21–A13 A21–A13 A21–A0 A21–A0
A12–A0 A23–A11
1 1 12 bit A21–A12 A21–A12 A21–A0 A21–A0
A11–A0 A23–A12
In addition to ordinary read and write accesses, burst mode access using high speed page mode is
supported.