Renesas SH7041 Series, Hardware Manual, Page: 307 / 923

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Table 11.11 Transfer Conditions and Register Set Values for Transfer between A/D
Converter (A/D1) and Internal Memory
Transfer Conditions Register Value
Transfer source: on-chip A/D converter (A/D1) SAR2 H'FFFF8408
Transfer destination: internal memory DAR2 H'FFFFF000
Transfer count: 128 times (reload count 32 times) DMATCR2 H'00000080
Transfer source address: incremented CHCR2 H'00085B25
Transfer target address: incremented
Transfer request source: A/D converter (A/D1)
Bus mode: burst
Transfer unit: byte
Interrupt request generated at end of transfer
Channel priority sequence: 0>2>3>1 DMAOR H'0101
When address reload is on, the SAR value returns to its initially established value every four
transfers. In the above example, when a transfer request is input from the A/D converter (A/D1),
the byte size data is first read in from the H'FFFF8408 register and that data is written to the on-
chip memory address H'FFFFF001. Because a byte size transfer was performed, the SAR and
DAR values at this point are H'FFFF8409 and H'FFFFF001, respectively. Also, because this is a
burst transfer, the bus rights remain secured, so continuous data transfer is possible.
When four transfers are completed, if the address reload is off, execution continues with the fifth
and sixth transfers and the SAR value continues to increment from H'FFFF840B to H'FFFF840C
to H'FFFF840D and so on. However, when the address reload is on, the DMAC transfer is halted
upon completion of the fourth transfer and the bus right request signal to the CPU is cleared. At
this time, the values stored in SAR are not H'FFFF840B–H'FFFF840C, but H'FFFF840B–
H'FFFF8408, a return to the initially established address. The DAR value always continues to be
decremented regardless of whether the address reload is on or off.
The DMAC internal status, due to the above operation after completion of the fourth transfer, is
indicated in table 11.12 for both address reload on and off.