Renesas SH7041 Series, Hardware Manual, Page: 608 / 923

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16.1.4 Register Configuration
Table 16.2 shows the register configuration of the mid-speed A/D converter.
Table 16.2 Register Configuration
Name Abbreviation R/W Initial Value Address Access Size
A/D0 data register AH ADDRA0H R H'00 H'FFFF8400 8, 16
A/D0 data register AL ADDRA0L R H'00 H'FFFF8401 8
A/D0 data register BH ADDRB0H R H'00 H'FFFF8402 8, 16
A/D0 data register BL ADDRB0L R H'00 H'FFFF8403 8
A/D0 data register CH ADDRC0H R H'00 H'FFFF8404 8, 16
A/D0 data register CL ADDRC0L R H'00 H'FFFF8405 8
A/D0 data register DH ADDRD0H R H'00 H'FFFF8406 8, 16
A/D0 data register DL ADDRD0L R H'00 H'FFFF8407 8
A/D0 control/status register ADCSR0 R/(W)
*
H'00 H'FFFF8410 8, 16
A/D0 control register ADCR0 R/W H'7F H'FFFF8412 8, 16
A/D1 data register AH ADDRA1H R H'00 H'FFFF8408 8, 16
A/D1 data register AL ADDRA1L R H'00 H'FFFF8409 8
A/D1 data register BH ADDRB1H R H'00 H'FFFF840A 8, 16
A/D1 data register BL ADDRB1L R H'00 H'FFFF840B 8
A/D1 data register CH ADDRC1H R H'00 H'FFFF840C 8, 16
A/D1 data register CL ADDRC1L R H'00 H'FFFF840D 8
A/D1 data register DH ADDRD1H R H'00 H'FFFF840E 8, 16
A/D1 data register DL ADDRD1L R H'00 H'FFFF840F 8
A/D1 control/status register ADCSR1 R/(W)
*
H'00 H'FFFF8411 8
A/D1 control register ADCR1 R/W H'7F H'FFFF8413 8
Note: * Only 0 can be written to bit 7 to clear the flag.