Renesas SH7041 Series, Hardware Manual, Page: 159 / 923

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Table 7.1 Register Configuration
Name Abbr. R/W
Initial
Value
Address
Access
Size
User break address register H UBARH R/W H'0000 H'FFFF8600 8, 16, 32
User break address register L UBARL R/W H'0000 H'FFFF8602 8, 16, 32
User break address mask register H UBAMRH R/W H'0000 H'FFFF8604 8, 16, 32
User break address mask register L UBAMRL R/W H'0000 H'FFFF8606 8, 16, 32
User break bus cycle register UBBR R/W H'0000 H'FFFF8608 8, 16, 32
7.2 Register Descriptions
7.2.1 User Break Address Register (UBAR)
The user break address register (UBAR) consists of user break address register H (UBARH) and
user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH
stores the upper bits (bits 31–16) of the address of the break condition, while UBARL stores the
lower bits (bits 15–0). Resets and hardware standbys initialize both UBARH and UBARL to
H'0000. They are not initialized in manual reset or software standby mode.
UBARH:
Bit: 15 14 13 12 11 10 9 8
UBARH UBA31 UBA30 UBA29 UBA28 UBA27 UBA26 UBA25 UBA24
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
UBARH UBA23 UBA22 UBA21 UBA20 UBA19 UBA18 UBA17 UBA16
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W