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Renesas SH7041 Series Hardware Manual Download Page 166

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7.3.2

Break on On-Chip Memory Instruction Fetch Cycle

On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in 1 bus cycle.
Therefore, 2 instructions can be retrieved in 1 bus cycle when fetching instructions from on-chip
memory. At such times, only 1 bus cycle is generated, but by setting the start addresses of both
instructions in the user break address register (UBAR) it is possible to cause independent breaks.
In other words, when wanting to effect a break using the latter of two addresses retrieved in 1 bus
cycle, set the start address of that instruction in UBAR. The break will occur after execution of the
former instruction.

7.3.3

Program Counter (PC) Values Saved

Break on Instruction Fetch (Before Execution): The program counter (PC) value saved to the
stack in user break interrupt exception processing is the address that matches the break condition.
The user break interrupt is generated before the fetched instruction is executed. If a break
condition is set in an instruction fetch cycle placed immediately after a delayed branch instruction
(delay slot), or on an instruction that follows an interrupt-disabled instruction, however, the user
break interrupt is not accepted immediately, but the break condition establishing instruction is
executed. The user break interrupt is accepted after execution of the instruction that has accepted
the interrupt. In this case, the PC value saved is the start address of the instruction that will be
executed after the instruction that has accepted the interrupt.

Break on Data Access (CPU/Peripheral): The program counter (PC) value is the top address of
the next instruction after the last instruction executed before the user break exception processing
started. When data access (CPU/peripheral) is set as a break condition, the place where the break
will occur cannot be specified exactly. The break will occur at the instruction fetched close to
where the data access that is to receive the break occurs.

7.4

Use Examples

7.4.1

Break on CPU Instruction Fetch Cycle

1. Register settings:

UBARH = H'0000
UBARL = H'0404
UBBR = H'0054

Conditions set:

Address: H'00000404
Bus cycle: CPU, instruction fetch, read
(operand size not included in conditions)

A user break interrupt will occur before the instruction at address H'00000404. If it is possible for
the instruction at H'00000402 to accept an interrupt, the user break exception processing will be
executed after execution of that instruction. The instruction at H'00000404 is not executed. The
PC value saved is H'00000404.

Summary of Contents for SH7041 Series

Page 1: ...Rev 6 00 2003 5 26 SH7040 SH7041 SH7042 SH7043 SH7044 SH7045 Group Hardware Manual 32 The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of revisions and additions Details should always be checked by referring to the relevant text ...

Page 2: ......

Page 3: ...Renesas 32 Bit RISC Microcomputer SuperH RISC engine Family SH7040 Series CPU Core SH 2 SH7040 SH7041 SH7042 SH7043 SH7044 SH7045 Group Hardware Manual REJ09B0044 0600O ...

Page 4: ...bed here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corporation by various means including the Renesas Technology Corporation Semiconductor home page http www renesas com 4 W...

Page 5: ...s an improvement in CPU performance during external memory access In addition the SH7040 series includes on chip peripheral functions necessary for system configuration such as large capacity ROM and RAM timers a serial communication interface SCI an A D converter an interrupt controller and I O ports Memory or peripheral LSIs can be connected efficiently with an external memory access support fun...

Page 6: ......

Page 7: ... V HD64F7045F28 See 256 kB Flash Memory See Electrical Characteristics SH7041A A mask 64 kB 32 bits 4LSB Mid Speed QFP2020 144 QFP2020 144Cu 20 C to 75 C 28 MHz 16 MHz 28 MHz 16 MHz 5 V 3 3 V 5 V 3 3 V HD6437041AF28 HD6437041AVF16 HD6437041ACF28 HD6437041AVCF16 See 64 kB Mask ROM See Electrical Characteristics SH7042A A mask 128 kB 16 bits 4LSB Mid Speed QFP2020 112 TQFP1414 120 QFP2020 112Cu 20 C...

Page 8: ...ation Register DMAOR 226 Description amended Bits 15 10 Reserved bits Data are 0 when read The write value always be 0 227 Description amended Bits 7 3 Reserved bits Data are 0 when read The write value always be 0 11 3 3 Channel Priority Figure 11 3 Round Robin Mode 233 Figure amended Channel 0 is given the lowest priority 12 4 5 Cascade Connection Mode Figure 12 23 Cascade Connection Operation E...

Page 9: ... cont 491 Table amended Bit Rate 27 0336 Bits s n N Error 110 3 119 0 00 150 3 87 0 00 300 2 175 0 00 600 1 87 0 00 1200 1 175 0 00 2400 1 87 0 00 4800 0 175 0 00 9600 0 87 0 00 14400 0 58 0 56 19200 0 43 0 00 28800 0 28 1 15 31250 0 26 0 12 38400 0 21 0 00 Table 14 4 Bit Rates and BRR Settings in Clocked Synchronous Mode cont 495 Table amended 3 5M 0 1 5M 0 0 7M 0 0 14 3 4 Clock Synchronous Opera...

Page 10: ...his LSI 10µF 0 01µF 100Ω Rin 2 0 1µF 1 1 16 7 2 Handling of Analog Input Pins Figure 16 8 Example of Analog Input Pin Protection Circuit 585 Note amended Notes Numbers are only to be noted as reference value 19 2 Port A Table 19 2 Port A FP 144 Version 649 Table amended PA16 I O AH output PA16 I O AH output PA16 I O PA15 I O CK output PA15 I O CK output PA15 I O CK output 21 2 2 Socket Adapter Pin...

Page 11: ...2 Figure amended 2 nF 0 1 µF 100 Ω Figure 21 4 SH7043 Pin and HN27C101 Pin Correspondence 144 Pin Version 673 Figure amended 100 Ω 0 1 µF 2 nF 22 2 2 Mode Transition Diagram Figure 22 2 Flash Memory Mode Transitions 683 Note amended Execute transition between the user mode and user program mode while the CPU is not programming or erasing the flash memory ...

Page 12: ...g 0 Verify Increment address Programming failure OK Clear SWE bit in FLMCR1 n 1000 n n 1 Start 3 3 4 End of programming Enable WDT Disable WDT Reprogram data computation Transfer reprogram data to reprogram data area Wait 10 µs Clear PV1 2 bit in FLMCR1 2 Wait 4 µs Dummy write of H FF to verify address Wait 2 µs Set PV1 2 bit in FLMCR1 2 Wait 4 µs Clear PSU1 2 bit in FLMCR1 2 Wait 10 µs Clear P1 2...

Page 13: ...n FLMCR1 2 Clear SWE bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n 60 NG NG NG NG OK OK OK OK n n 1 Increment address Notes 1 Preprogramming setting erase block data to all 0 is not necessary 2 Verify data is read in 32 bit longword units 3 Set only one bit in EBR1 2 More than one bit cannot...

Page 14: ...en thesetup times shown here are provided the signals are considered to have produced changes at clock rise for RES MRES BREQ or clock fall for NMI and IRQ7 IRQ0 If the setup times are not provided recognition is delayed until the next clock rise or fall 25 3 3 Bus Timing Figure 25 12 DRAM Cycle Normal Mode 1 Wait TPC 0 RCD 0 763 Figure amended Tcw1 Tc2 tCASD1 tCAC tRAC tAA tRDS Column address Fig...

Page 15: ...ed Tcw1 Tcw2 tCASD1 tCAC tAA Column 25 3 5 Multifunction Timer Pulse Unit Timing Figure 25 23 MTU I O Timing 770 Figure amended tTOCD Figure 25 24 MTU Clock Input Timing 770 Figure amended tTCKS 25 3 11 Measuring Conditions for AC Characteristics Figure 25 33 Output Load Circuit 778 Title amended Output Load Circuit ...

Page 16: ... only 3 2 mA in the A mask version of MASK products 26 3 2 Control Signal Timing Table 26 5 Control Signal Timing 786 Note amended Notes 1 SH7042 43 ZTAT excluding A mask are 3 2V 2 The RES MRES NMI BREQ and IRQ7 IRQ0 signals are asynchronous inputs but when the setup times shown here are provided the signals are considered to have produced changes at clock rise for RES MRES BREQ or clock fall for...

Page 17: ...igure 26 14 DRAM Cycle Normal Mode 3 Waits TPC 1 RCD 1 796 Figure amended Tcw1 Tcw2 tCASD1 tCAC tAA tCASD1 Column address tRAC 26 3 5 Multifunction Timer Pulse Unit Timing Figure 26 23 MTU I O Timing 802 Figure amended CK tTOCD Output compare output 26 3 11 Measurement Conditions for AC Characteristics Figure 26 33 Output Load Circuit 810 Title amended Output Load Circuit ...

Page 18: ...e Clock CK O O H 1 O O O System RES I I I I I I control MRES Z 4 I Z I I Z WDTOVF O 3 O 3 O O O O BREQ Z 4 I Z I I I BACK Z 4 O Z O L L Interrupt NMI I I I I I I IRQ0 IRQ7 Z 4 I Z I I Z IRQOUT PD30 Z 4 O H 1 H O H 1 IRQOUT PE15 Z 4 O Z H O Z Address bus A0 A21 O 2 O Z O Z Z Data bus D0 D31 Z 4 I O Z I O Z Z Bus WAIT Z 4 I Z I Z Z control RD WR RAS Z 4 O O O Z Z CASH CASL CASLH CASLL Z 4 O O O Z Z ...

Page 19: ...11 PE15 Z 4 I O Z K I O Z PF0 PF17 Z I Z I I Z Notes 1 There are instances where bus right release and transition to software standby mode occur simultaneously due to the timing between BREQ and internal operations In such cases standby mode results but the standby state may be different The initial pin states depend on the mode See section 18 Pin Function Controller PFC for details 2 I Input O Ou...

Page 20: ...Q Z 4 I Z I I I BACK Z 4 O Z O L L Interrupt NMI I I I I I I IRQ0 IRQ7 Z 4 I Z I I Z IRQOUT Z 4 O Z H O Z Address bus A0 A21 O 2 O Z O Z Z Data bus D0 D31 Z 4 I O Z I O Z Z Bus WAIT Z 4 I Z I Z Z control RDWR RAS Z 4 O O O Z Z CASH CASL Z 4 O O O Z Z RD H O Z O Z Z CS0 CS1 H O Z O Z Z CS2 CS3 Z 4 O Z O Z Z WRH WRL H O Z O Z Z AH Z 4 O Z O Z Z DMAC DACK0 DACK1 Z 4 O Z O O Z DRAK0 DRAK1 Z 4 O Z O O ...

Page 21: ...ces where bus right release and transition to software standby mode occur simultaneously due to the timing between BREQ and internal operations In such cases standby mode results but the standby state may be different The initial pin states depend on the mode See section 18 Pin Function Controller PFC for details 2 I Input O Output H High level output L Low level output Z High impedance K Input pi...

Page 22: ...44 QFP2020 144Cu 1 QFP2020 144Cu 1 HD6417041AF28 HD6417041AVF16 HD6417041ACF28 HD6417041AVCF16 Z TAT version HD6477042F28 HD6477042VF16 HD6477042F28 HD6477042VF16 QFP2020 112 QFP2020 112 HD6477042F28 HD6477042VF16 Product Type SH7042A Z TAT version A MASK HD6477042AF28 HD6477042AVF16 HD6477042AVX16 HD6477042ACF28 HD6477042AVCF16 HD6477042AF28 HD6477042AVF16 HD6477042AVX16 HD6477042ACF28 HD6477042A...

Page 23: ...ues of Registers 47 2 2 Data Formats 48 2 2 1 Data Format in Registers 48 2 2 2 Data Format in Memory 48 2 2 3 Immediate Data Format 48 2 3 Instruction Features 49 2 3 1 RISC Type Instruction Set 49 2 3 2 Addressing Modes 52 2 3 3 Instruction Format 56 2 4 Instruction Set by Classification 59 2 5 Processing States 72 2 5 1 State Transitions 72 2 5 2 Power Down State 74 Section 3 Operating Modes 77...

Page 24: ...t Exception Processing 94 5 5 Exceptions Triggered by Instructions 94 5 5 1 Trap Instructions 95 5 5 2 Illegal Slot Instructions 95 5 5 3 General Illegal Instructions 96 5 6 When Exception Sources Are Not Accepted 96 5 6 1 Immediately after a Delayed Branch Instruction 96 5 6 2 Immediately after an Interrupt Disabled Instruction 96 5 7 Stack Status after Exception Processing Ends 97 5 8 Notes on U...

Page 25: ...C Activating Sources 118 6 6 4 Treating CPU Interrupt Sources but Not DTC or DMAC Activating Sources 118 Section 7 User Break Controller UBC 119 7 1 Overview 119 7 1 1 Features 119 7 1 2 Block Diagram 119 7 1 3 Register Configuration 120 7 2 Register Descriptions 121 7 2 1 User Break Address Register UBAR 121 7 2 2 User Break Address Mask Register UBAMR 122 7 2 3 User Break Bus Cycle Register UBBR...

Page 26: ...n 143 8 3 2 Activating Sources 145 8 3 3 DTC Vector Table 145 8 3 4 Register Information Placement 148 8 3 5 Normal Mode 149 8 3 6 Repeat Mode 149 8 3 7 Block Transfer Mode 150 8 3 8 Operation Timing 151 8 3 9 DTC Execution State Counts 151 8 3 10 DTC Usage Procedure 153 8 3 11 DTC Use Example 153 8 4 Cautions on Use 154 Section 9 Cache Memory CAC 155 9 1 Overview 155 9 1 1 Features 155 9 1 2 Bloc...

Page 27: ...ccessing Ordinary Space 185 10 3 1 Basic Timing 185 10 3 2 Wait State Control 186 10 3 3 CS Assert Period Extension 188 10 4 DRAM Access 189 10 4 1 DRAM Direct Connection 189 10 4 2 Basic Timing 190 10 4 3 Wait State Control 191 10 4 4 Burst Operation 195 10 4 5 Refresh Timing 197 10 5 Address Data Multiplex I O Space Access 199 10 5 1 Basic Timing 199 10 5 2 Wait State Control 200 10 5 3 CS Asser...

Page 28: ...y Order 246 11 3 10 Number of Bus Cycle States and DREQ Pin Sample Timing 246 11 3 11 Source Address Reload Function 263 11 3 12 DMA Transfer Ending Conditions 264 11 3 13 DMAC Access from CPU 265 11 4 Examples of Use 265 11 4 1 Example of DMA Transfer between On Chip SCI and External Memory 265 11 4 2 Example of DMA Transfer between External RAM and External Device with DACK 266 11 4 3 Example of...

Page 29: ...2 3 1 16 Bit Registers 322 12 3 2 8 Bit Registers 323 12 4 Operation 324 12 4 1 Overview 324 12 4 2 Basic Functions 325 12 4 3 Synchronous Operation 330 12 4 4 Buffer Operation 333 12 4 5 Cascade Connection Mode 336 12 4 6 PWM Mode 337 12 4 7 Phase Counting Mode 341 12 4 8 Reset Synchronized PWM Mode 348 12 4 9 Complementary PWM Mode 352 12 5 Interrupts 377 12 5 1 Interrupt Sources and Priority Ra...

Page 30: ...ons on Using the Chopping Function in Complementary PWM Mode or Reset Synchronous PWM Mode A Mask Excluded 409 12 7 21 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode A Mask Excluded 409 12 7 22 Cautions on Restarting with Sync Clear of Another Channel in Complementary PWM Mode A Mask Excluded 410 12 8 MTU Output Pin Initialization 411 12 8 1 Operating Modes 411 12 8 2 Reset Sta...

Page 31: ...2 CKS0 Bit Values 466 13 4 3 Changing between Watchdog Timer Interval Timer Modes 466 13 4 4 System Reset With WDTOVF 467 13 4 5 Internal Reset with the Watchdog Timer 467 Section 14 Serial Communication Interface SCI 469 14 1 Overview 469 14 1 1 Features 469 14 1 2 Block Diagram 470 14 1 3 Pin Configuration 471 14 1 4 Register Configuration 471 14 2 Register Descriptions 472 14 2 1 Receive Shift ...

Page 32: ...k 537 15 1 Overview 537 15 1 1 Features 537 15 1 2 Block Diagram 538 15 1 3 Pin Configuration 538 15 1 4 Register Configuration 539 15 2 Register Descriptions 540 15 2 1 A D Data Registers A H ADDRA ADDRH 540 15 2 2 A D Control Status Register ADCSR 541 15 2 3 A D Control Register ADCR 544 15 3 Bus Master Interface 545 15 4 Operation 548 15 4 1 Select Single Mode 548 15 4 2 Select Scan Mode 549 15...

Page 33: ...atures 587 17 1 2 Block Diagram 587 17 1 3 Register Configuration 589 17 2 Register Descriptions 590 17 2 1 Compare Match Timer Start Register CMSTR 590 17 2 2 Compare Match Timer Control Status Register CMCSR 591 17 2 3 Compare Match Timer Counter CMCNT 592 17 2 4 Compare Match Timer Constant Register CMCOR 593 17 3 Operation 593 17 3 1 Period Count Operation 593 17 3 2 CMCNT Count Timing 594 17 ...

Page 34: ...s 1 2 PECR1 and PECR2 638 18 3 15 IRQOUT Function Control Register IFCR 643 18 4 Cautions on Use 645 Section 19 I O Ports I O 647 19 1 Overview 647 19 2 Port A 647 19 2 1 Register Configuration 650 19 2 2 Port A Data Register H PADRH 650 19 2 3 Port A Data Register L PADRL 651 19 3 Port B 652 19 3 1 Register Configuration 652 19 3 2 Port B Data Register PBDR 653 19 4 Port C 654 19 4 1 Register Con...

Page 35: ...689 22 4 Register Configuration 689 22 5 Description of Registers 690 22 5 1 Flash Memory Control Register 1 FLMCR1 690 22 5 2 Flash Memory Control Register 2 FLMCR2 692 22 5 3 Erase Block Register 1 EBR1 695 22 5 4 Erase Block Register 2 EBR2 695 22 5 5 RAM Emulation Register RAMER 696 22 6 On Board Programming Mode 698 22 6 1 Boot Mode 699 22 6 2 User Program Mode 703 22 7 Programming Erasing Fl...

Page 36: ...4 1 Overview 743 24 1 1 Power Down States 743 24 1 2 Related Register 744 24 2 Standby Control Register SBYCR 744 24 3 Sleep Mode 745 24 3 1 Transition to Sleep Mode 745 24 3 2 Canceling Sleep Mode 745 24 4 Standby Mode 745 24 4 1 Transition to Standby Mode 745 24 4 2 Canceling the Standby Mode 747 24 4 3 Standby Mode Application Example 748 Section 25 Electrical Characteristics 5V 28 7 MHz Versio...

Page 37: ...ontroller Timing 800 26 3 5 Multifunction Timer Pulse Unit Timing 802 26 3 6 I O Port Timing 803 26 3 7 Watchdog Timer Timing 804 26 3 8 Serial Communication Interface Timing 805 26 3 9 High speed A D Converter Timing excluding A mask 806 26 3 10 Mid speed Converter Timing A mask 808 26 3 11 Measurement Conditions for AC Characteristic 810 26 4 A D Converter Characteristics 811 Appendix A On Chip ...

Page 38: ...xvi ...

Page 39: ... chip peripheral functions necessary for system configuration such as large capacity ROM and RAM timers a serial communication interface SCI an A D converter an interrupt controller and I O ports Memory or peripheral LSIs can be connected efficiently with an external memory access support function This greatly reduces system cost In addition to the masked ROM versions of the SH7040 series the SH70...

Page 40: ...length 1 longword 2 instruction lengths 256 entry cache tags Direct map method On chip ROM RAM and on chip I O areas not objects of cache Used in common with on chip RAM 2 kbytes of on chip RAM used as address array data array when cache is enabled Interrupt Controller INTC Nine external interrupt pins NMI IRQ0 IRQ7 Forty three internal interrupt sources forty four for A mask Sixteen programmable ...

Page 41: ... the data at the transfer source address as an address and transfers the data at that address to the transfer destination address Data Transfer Controller DTC Data transfer independent of the CPU possible through peripheral I O interrupt requests Transfer mode can be set for each interrupt factor transfer mode set in memory Multiple data transfers possible for one activating factor Abundant transf...

Page 42: ...hase PWM waveforms Phase calculation mode 2 phase encoder calculation processing Compare Match Timer CMT Two Channels 16 bit free running counter One compare register Generates an interrupt request upon compare match Watchdog Timer WDT One Channel Watchdog timer or interval timer Count overflow can generate an internal reset external signal or interrupt Serial Communication Interface SCI Two Chann...

Page 43: ...apacity On Chip Memory ROM 128 kbytes PROM 256 kbytes 128 kbytes 64 kbytes mask ROM 256 kbytes flash ROM SH7044 SH7045 256 kbytes flash ROM mask ROM SH7042 SH7043 128 kbytes ZTAT mask ROM SH7040 SH7041 64 kbytes mask ROM RAM 4 kbytes 2 kbytes when cache is used Operating Modes Operating modes Expanded mode with ROM disabled Expanded mode with ROM enabled Single chip mode Processing states Program ...

Page 44: ...6 ...

Page 45: ... on transfer requests Change the Usage Notes See Mid Speed A D Converter See 256 kB Flash Memory See Electrical Characteristics MASK SH7040A A mask 64 kB 16 bits 4LSB Mid Speed QFP2020 112 TQFP1414 120 QFP2020 112Cu 20 C to 75 C 28 MHz 16 MHz 16 MHz 28 MHz 16 MHz 5 V 3 3 V 3 3 V 5 V 3 3 V HD6437040AF28 HD6437040AVF16 HD6437040AVX16 HD6437040ACF28 HD6437040AVCF16 Change the interrupt vectors relate...

Page 46: ...8 ...

Page 47: ... on transfer requests Change the Usage Notes See Mid Speed A D Converter See 256 kB Mask ROM See Electrical Characteristics ROM less SH7040A A mask 16 bits 4LSB Mid Speed QFP2020 112 TQFP1414 120 QFP2020 112Cu 20 C to 75 C 28 MHz 16 MHz 16 MHz 28 MHz 16 MHz 5 V 3 3 V 3 3 V 5 V 3 3 V HD6417040AF28 HD6417040AVF16 HD6417040AVX16 HD6417040ACF28 HD6417040AVCF16 Change the interrupt vectors related A D ...

Page 48: ...10 ...

Page 49: ...DREQ1 IRQ1 PA4 TXD1 PA3 RXD1 PA2 SCK0 DREQ0 IRQ0 PA1 TXD0 PA0 RXD0 PE15 TIOC4D DACK1 IRQOUT PE14 TIOC4C DACK0 AH PE13 TIOC4B MRES PE12 TIOC4A PE11 TIOC3D PE10 TIOC3C PE9 TIOC3B PE8 TIOC3A PE7 TIOC2B PE6 TIOC2A PE5 TIOC1B PE4 TIOC1A PE3 TIOC0D DRAK1 PE2 TIOC0C DREQ1 PE1 TIOC0B DRAK0 PE0 TIOC0A DREQ0 Peripheral address bus Peripheral data bus Internal address bus Internal upper data bus Internal low...

Page 50: ...A5 SCK1 DREQ1 IRQ1 PA4 TXD1 PA3 RXD1 PA2 SCK0 DREQ0 IRQ0 PA1 TXD0 PA0 RXD0 PE15 TIOC4D DACK1 IRQOUT PE14 TIOC4C DACK0 AH PE13 TIOC4B MRES PE12 TIOC4A PE11 TIOC3D PE10 TIOC3C PE9 TIOC3B PE8 TIOC3A PE7 TIOC2B PE6 TIOC2A PE5 TIOC1B PE4 TIOC1A PE3 TIOC0D DRAK1 PE2 TIOC0C DREQ1 PE1 TIOC0B DRAK0 PE0 TIOC0A DREQ0 PLL PF7 AN7 PF6 AN6 PF5 AN5 PF4 AN4 PF3 AN3 PF2 AN2 PF1 AN1 PF0 AN0 Flash ROM PROM mask ROM ...

Page 51: ... D10 PD11 D11 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 PD12 D12 VSS PD13 D13 PD14 D14 PD15 D15 PA0 RXD0 PA1 TXD0 PA2 SCK0 DREQ0 IRQ0 PA3 RXD1 PA4 TXD1 PA5 SCK1 DREQ1 IRQ1 PA7 TCLKB CS3 PA8 TCLKC IRQ2 PA10 CS0 PA11 CS1 VSS PA12 WRL VCC PA13 WRH WDTOVF PA14 RD VSS PB9 IRQ7 A21 ADTRG PB8 IRQ6 A20 WAIT PB7 IRQ5 A19 BREQ PB6 IRQ4 A18 BACK PA6 TCLKA CS2 PA9 TCL...

Page 52: ...Vss PLLCAP PLLVcc MD0 MD1 Vcc NMI MD2 EXTAL MD3 XTAL Vss PD0 D0 PD1 D1 PD2 D2 PD3 D3 PD4 D4 Vcc PD5 D5 PD6 D6 PD7 D7 Vss PD8 D8 PD9 D9 PD10 D10 PD11 D11 NC NC PE13 TIOC4B MRES PE12 TIOC4A PE11 TIOC3D Vss PE10 TIOC3C PE9 TIOC3B PE8 TIOC3A PE7 TIOC2B PE6 TIOC2A Vcc PE5 TIOC1B Vss AVcc PF7 AN7 PF6 AN6 AVss PF5 AN5 PF4 AN4 PF3 AN3 PF2 AN2 PF1 AN1 PF0 AN0 Vss PE4 TIOC1A PE3 TIOC0D DRAK1 PE2 TIOC0C DREQ...

Page 53: ...47 46 45 44 43 42 41 40 39 38 37 72 PD16 D16 IRQ0 VSS PD17 D17 IRQ1 PD18 D18 IRQ2 PD19 D19 IRQ3 PD20 D20 IRQ4 PD21 D21 IRQ5 PD22 D22 IRQ6 PD23 D23 IRQ7 VCC PD24 D24 DREQ0 PD27 D27 DACK1 PD28 D28 CS2 PD29 D29 CS3 VSS PA6 TCLKA CS2 PA7 TCLKB CS3 PA8 TCLKC IRQ2 PA9 TCLKD IRQ3 PA11 CS1 PA12 WRL PA13 WRH PD30 D30 IRQOUT PD31 D31 ADTRG VSS PD25 D25 DREQ1 PD26 D26 DACK0 PA10 CS0 WDTOVF PA14 RD PB9 IRQ7 A...

Page 54: ... VSS 4 PC0 A0 A0 5 PC1 A1 A1 6 PC2 A2 A2 7 PC3 A3 A3 8 PC4 A4 A4 9 PC5 A5 A5 10 PC6 A6 A6 11 PC7 A7 A7 12 PC8 A8 A8 13 PC9 A9 NC 14 PC10 A10 A10 15 PC11 A11 A11 16 PC12 A12 A12 17 PC13 A13 A13 18 PC14 A14 A14 19 PC15 A15 A15 20 PB0 A16 A16 21 VCC VCC 22 PB1 A17 NC 23 VSS VSS 24 PB2 IRQ0 POE0 RAS NC 25 PB3 IRQ1 POE1 CASL OE 26 PB4 IRQ2 POE2 CASH PGM 27 VSS VSS 28 PB5 IRQ3 POE3 RDWR VCC ...

Page 55: ...S 34 PA14 RD NC 35 WDTOVF NC 36 PA13 WRH NC 37 VCC VCC 38 PA12 WRL NC 39 VSS VSS 40 PA11 CS1 NC 41 PA10 CS0 NC 42 PA9 TCLKD IRQ3 NC 43 PA8 TCLKC IRQ2 NC 44 PA7 TCLKB CS3 NC 45 PA6 TCLKA CS2 NC 46 PA5 SCK1 DREQ1 IRQI NC 47 PA4 TXD1 NC 48 PA3 RXD1 NC 49 PA2 SCK0 DREQ0 IRQ0 NC 50 PA1 TXD0 NC 51 PA0 RXD0 NC 52 PD15 D15 NC 53 PD14 D14 NC 54 PD13 D13 NC 55 VSS VSS 56 PD12 D12 NC 57 PD11 D11 NC 58 PD10 D...

Page 56: ...6 D6 D6 64 PD5 D5 D5 65 VCC VCC 66 PD4 D4 D4 67 PD3 D3 D3 68 PD2 D2 D2 69 PD1 D1 D1 70 PD0 D0 D0 71 VSS VSS 72 XTAL NC 73 MD3 VCC 74 EXTAL VSS 75 MD2 VCC 76 NMI A9 77 VCC VCC 78 MD1 VCC 79 MD0 VCC 80 PLLVCC VCC 81 PLLCAP VSS 82 PLLVSS VSS 83 PA15 CK NC 84 RES VPP 85 PE0 TIOC0A DREQ0 NC 86 PE1 TIOC0B DRAK0 NC 87 PE2 TIOC0C DREQ1 NC 88 PE3 TIOC0D DRAK1 NC ...

Page 57: ...SS 92 PF1 AN1 VSS 93 PF2 AN2 VSS 94 PF3 AN3 VSS 95 PF4 AN4 VSS 96 PF5 AN5 VSS 97 AVSS VSS 98 PF6 AN6 VSS 99 PF7 AN7 VSS 100 AVCC VCC 101 VSS VSS 102 PE5 TIOC1B NC 103 VCC VCC 104 PE6 TIOC2A NC 105 PE7 TIOC2B NC 106 PE8 TIOC3A NC 107 PE9 TIOC3B NC 108 PE10 TIOC3C NC 109 VSS VSS 110 PE11 TIOC3D NC 111 PE12 TIOC4A NC 112 PE13 TIOC4B MRES NC ...

Page 58: ... 6 PC1 A1 A1 7 PC2 A2 A2 8 PC3 A3 A3 9 PC4 A4 A4 10 PC5 A5 A5 11 PC6 A6 A6 12 PC7 A7 A7 13 PC8 A8 A8 14 PC9 A9 NC 15 PC10 A10 A10 16 PC11 A11 A11 17 PC12 A12 A12 18 PC13 A13 A13 19 PC14 A14 A14 20 PC15 A15 A15 21 PB0 A16 A16 22 VCC VCC 23 PB1 A17 NC 24 VSS VSS 25 PB2 IRQ0 POE0 RAS NC 26 PB3 IRQ1 POE1 CASL OE 27 PB4 IRQ2 POE2 CASH PGM 28 VSS VSS 29 PB5 IRQ3 POE3 RDWR VCC 30 NC NC 31 NC NC ...

Page 59: ... VSS 37 PA14 RD NC 38 WDTOVF NC 39 PA13 WRH NC 40 VCC VCC 41 PA12 WRL NC 42 VSS VSS 43 PA11 CS1 NC 44 PA10 CS0 NC 45 PA9 TCLKD IRQ3 NC 46 PA8 TCLKC IRQ2 NC 47 PA7 TCLKB CS3 NC 48 PA6 TCLKA CS2 NC 49 PA5 SCK1 DREQ1 IRQ1 NC 50 PA4 TXD1 NC 51 PA3 RXD2 NC 52 PA2 SCK0 DREQ0 IRQ0 NC 53 PA1 TXD0 NC 54 PA0 RXD0 NC 55 PD15 D15 NC 56 PD14 D14 NC 57 PD13 D13 NC 58 VSS VSS 59 PD12 D12 NC 60 NC NC 61 NC NC 62 ...

Page 60: ...VSS VSS 67 PD7 D7 D7 68 PD6 D6 D6 69 PD5 D5 D5 70 VCC VCC 71 PD4 D4 D4 72 PD3 D3 D3 73 PD2 D2 D2 74 PD1 D1 D1 75 PD0 D0 D0 76 VSS VSS 77 XTAL NC 78 MD3 VCC 79 EXTAL VSS 80 MD2 VCC 81 NMI A9 82 VCC VCC 83 MD1 VCC 84 MD0 VCC 85 PLLVCC VCC 86 PLLCAP VSS 87 PLLVSS VSS 88 PA15 CK NC 89 RES VPP 90 NC NC 91 NC NC 92 PE0 TIOC0A DREQ0 NC 93 PE1 TIOC0B DRAK0 NC ...

Page 61: ...SS VSS 98 PF0 AN0 VSS 99 PF1 AN1 VSS 100 PF2 AN2 VSS 101 PF3 AN3 VSS 102 PF4 AN4 VSS 103 PF5 AN5 VSS 104 AVSS VSS 105 PF6 AN6 VSS 106 PF7 AN7 VSS 107 AVCC VCC 108 VSS VSS 109 PE5 TIOC1B NC 110 NC NC 111 VCC VCC 112 PE6 TIOC2A NC 113 PE7 TIOC2B NC 114 PE8 TIOC3A NC 115 PE9 TIOC3B NC 116 PE10 TIOC3C NC 117 VSS VSS 118 PE11 TIOC3D NC 119 PE12 TIOC4A NC 120 PE13 TIOC4B MRES NC ...

Page 62: ...E15 TIOC4D DACK1 IRQOUT CE 6 VSS VSS 7 PC0 A0 A0 8 PC1 A1 A1 9 PC2 A2 A2 10 PC3 A3 A3 11 PC4 A4 A4 12 VCC VCC 13 PC5 A5 A5 14 VSS VSS 15 PC6 A6 A6 16 PC7 A7 A7 17 PC8 A8 A8 18 PC9 A9 NC 19 PC10 A10 A10 20 PC11 A11 A11 21 PC12 A12 A12 22 PC13 A13 A13 23 PC14 A14 A14 24 PC15 A15 A15 25 PB0 A16 A16 26 VCC VCC 27 PB1 A17 NC 28 VSS VSS 29 PA20 CASHL NC 30 PA19 BACK DRAK1 NC ...

Page 63: ...B6 IRQ4 A18 BACK NC 38 PB7 IRQ5 A19 BREQ NC 39 PB8 IRQ6 A20 WAIT NC 40 VCC VCC 41 PB9 IRQ7 A21 ADTRG NC 42 VSS VSS 43 PA14 RD NC 44 WDTOVF NC 45 PD31 D31 ADTRG NC 46 PD30 D30 IRQOUT NC 47 PA13 WRH NC 48 PA12 WRL NC 49 PA11 CS1 NC 50 PA10 CS0 NC 51 PA9 TCLKD IRQ3 NC 52 PA8 TCLKC IRQ2 NC 53 PA7 TCLKB CS3 NC 54 PA6 TCLKA CS2 NC 55 VSS VSS 56 PD29 D29 CS3 NC 57 PD28 D28 CS2 NC 58 PD27 D27 DACK1 NC 59 ...

Page 64: ...RQ6 NC 66 PD21 D21 IRQ5 NC 67 PD20 D20 IRQ4 NC 68 PD19 D19 IRQ3 NC 69 PD18 D18 IRQ2 NC 70 PD17 D17 IRQ1 NC 71 VSS VSS 72 PD16 D16 IRQ0 NC 73 PD15 D15 NC 74 PD14 D14 NC 75 PD13 D13 NC 76 PD12 D12 NC 77 VCC VCC 78 PD11 D11 NC 79 VSS VSS 80 PD10 D10 NC 81 PD9 D9 NC 82 PD8 D8 NC 83 PD7 D7 D7 84 PD6 D6 D6 85 VCC VCC 86 PD5 D5 D5 87 VSS VSS 88 PD4 D4 D4 89 PD3 D3 D3 90 PD2 D2 D2 ...

Page 65: ...2 VCC 98 NMI A9 99 VCC VCC 100 PA16 AH NC 101 PA17 WAIT NC 102 MD1 VCC 103 MD0 VCC 104 PLLVCC VCC 105 PLLCAP VSS 106 PLLVSS VSS 107 PA15 CK NC 108 RES VPP 109 PE0 TIOC0A DREQ0 NC 110 PE1 TIOC0B DRAK0 NC 111 PE2 TIOC0C DREQ1 NC 112 VCC VCC 113 PE3 TIOC0D DRAK1 NC 114 PE4 TIOC1A NC 115 PE5 TIOC1B NC 116 PE6 TIOC2A NC 117 VSS VSS 118 PF0 AN0 VSS 119 PF1 AN1 VSS 120 PF2 AN2 VSS ...

Page 66: ...S VSS 125 PF6 AN6 VSS 126 PF7 AN7 VSS 127 AVref VCC 128 AVCC VCC 129 VSS VSS 130 PA0 RXD0 NC 131 PA1 TXD0 NC 132 PA2 SCK0 DREQ0 IREQ0 NC 133 PA3 RXD1 NC 134 PA4 TXD1 NC 135 VCC VCC 136 PA5 SCK1 DREQ1 IREQ1 NC 137 PE7 TIOC2B NC 138 PE8 TIOC3A NC 139 PE9 TIOC3B NC 140 PE10 TIOC3C NC 141 VSS VSS 142 PE11 TIOC3D NC 143 PE12 TIOC4A NC 144 PE13 TIOC4B MRES NC ...

Page 67: ...5 A5 A5 10 PC6 A6 A6 11 PC7 A7 A7 12 PC8 A8 A8 13 PC9 A9 A9 14 PC10 A10 A10 15 PC11 A11 A11 16 PC12 A12 A12 17 PC13 A13 A13 18 PC14 A14 A14 19 PC15 A15 A15 20 PB0 A16 A16 21 VCC VCC 22 PB1 A17 NC 23 VSS VSS 24 PB2 IRQ0 POE0 RAS NC 25 PB3 IRQ1 POE1 CASL NC 26 PB4 IRQ2 POE2 CASH A17 27 VSS VSS 28 PB5 IRQ3 POE3 RDWR NC 29 PB6 IRQ4 A18 BACK NC 30 PB7 IRQ5 A19 BREQ NC 31 PB8 IRQ6 A20 WAIT NC 32 PB9 IRQ...

Page 68: ...NC 41 PA10 CS0 NC 42 PA9 TCLKD IRQ3 CE 43 PA8 TCLKC IRQ2 OE 44 PA7 TCLKB CS3 WE 45 PA6 TCLKA CS2 NC 46 PA5 SCK1 DREQ1 IRQ1 VCC 47 PA4 TXD1 NC 48 PA3 RXD1 NC 49 PA2 SCK0 DREQ0 IRQ0 VCC 50 PA1 TXD0 VCC 51 PA0 RXD0 NC 52 PD15 D15 NC 53 PD14 D14 NC 54 PD13 D13 NC 55 VSS VSS 56 PD12 D12 NC 57 PD11 D11 NC 58 PD10 D10 NC 59 PD9 D9 NC 60 PD8 D8 NC 61 VSS VSS 62 PD7 D7 D7 63 PD6 D6 D6 64 PD5 D5 D5 ...

Page 69: ... MD2 76 NMI VCC 77 VCC FWP FWE 78 MD1 MD1 79 MD0 MD0 80 PLLVCC PLLVCC 81 PLLCAP PLLCAP 82 PLLVSS PLLVSS 83 PA15 CK NC 84 RES RES 85 PE0 TIOCA DREQ0 NC 86 PE1 TIOCB DRAK0 NC 87 PE2 TIOCC DREQ1 NC 88 PE3 TIOCD DRAK1 NC 89 PE4 TIOC1A NC 90 VSS VSS 91 PF0 AN0 VSS 92 PF1 AN1 VSS 93 PF2 AN2 VSS 94 PF3 AN3 VSS 95 PF4 AN4 VSS 96 PF5 AN5 VSS Note VCC in the mask version FWP in the F ZTAT version however FW...

Page 70: ...U Writer mode 97 AVSS VSS 98 PF6 AN6 VSS 99 PF7 AN7 VSS 100 AVCC VCC 101 VSS VSS 102 PE5 TIOC1B NC 103 VCC VCC 104 PE6 TIOC2A NC 105 PE7 TIOC2B NC 106 PE8 TIOC3A NC 107 PE9 TIOC3B NC 108 PE10 TIOC3C NC 109 VSS VSS 110 PE11 TIOC3D NC 111 PE12 TIOC4A NC 112 PE13 TIOC4B MRES NC ...

Page 71: ...10 PC3 A3 A3 11 PC4 A4 A4 12 VCC VCC 13 PC5 A5 A5 14 VSS VSS 15 PC6 A6 A6 16 PC7 A7 A7 17 PC8 A8 A8 18 PC9 A9 A9 19 PC10 A10 A10 20 PC11 A11 A11 21 PC12 A12 A12 22 PC13 A13 A13 23 PC14 A14 A14 24 PC15 A15 A15 25 PB0 A16 A16 26 VCC VCC 27 PB1 A17 NC 28 VSS VSS 29 PA20 CASHL NC 30 PA19 BACK DRAK1 NC 31 PB2 IRQ0 POE0 RAS NC 32 PB3 IRQ1 POE1 CASL NC 33 PA18 BREQ DRAK0 NC 34 PB4 IRQ2 POE2 CASH A17 35 V...

Page 72: ...T NC 47 PA13 WRH NC 48 PA12 WRL NC 49 PA11 CS1 NC 50 PA10 CS0 NC 51 PA9 TCLKD IRQ3 CE 52 PA8 TCLKC IRQ2 OE 53 PA7 TCLKB CS3 WE 54 PA6 TCLKA CS2 NC 55 VSS VSS 56 PD29 D29 CS3 NC 57 PD28 D28 CS2 NC 58 PD27 D27 DACK1 NC 59 PD26 D26 DACK0 NC 60 PD25 D25 DREQ1 NC 61 VSS VSS 62 PD24 D24 DREQ0 NC 63 VCC VCC 64 PD23 D23 IRQ7 NC 65 PD22 D22 IRQ6 NC 66 PD21 D21 IRQ5 NC 67 PD20 D20 IRQ4 NC 68 PD19 D19 IRQ3 N...

Page 73: ...C 83 PD7 D7 D7 84 PD6 D6 D6 85 VCC VCC 86 PD5 D5 D5 87 VSS VSS 88 PD4 D4 D4 89 PD3 D3 D3 90 PD2 D2 D2 91 PD1 D1 D1 92 PD0 D0 D0 93 VSS VSS 94 XTAL XTAL 95 MD3 MD3 96 EXTAL EXTAL 97 MD2 MD2 98 NMI VCC 99 VCC FWP FWE 100 PA16 AH NC 101 PA17 WAIT NC 102 MD1 MD1 103 MD0 MD0 104 PLLVCC PLLVCC 105 PLLCAP PLLCAP 106 PLLVSS PLLVSS 107 PA15 CK NC Note VCC in the mask version FWP in the F ZTAT version howev...

Page 74: ...VSS VSS 118 PF0 AN0 VSS 119 PF1 AN1 VSS 120 PF2 AN2 VSS 121 PF3 AN3 VSS 122 PF4 AN4 VSS 123 PF5 AN5 VSS 124 AVSS VSS 125 PF6 AN6 VSS 126 PF7 AN7 VSS 127 AVref VCC 128 AVCC VCC 129 VSS VSS 130 PA0 RXD0 NC 131 PA1 TXD0 VCC 132 PA2 SCK0 DREQ0 IRQ0 VCC 133 PA3 RXD1 NC 134 PA4 TXD1 NC 135 VCC VCC 136 PA5 SCK1 DREQ1 IRQ1 VCC 137 PE7 TIOC2B NC 138 PE8 TIOC3A NC 139 PE9 TIOC3B NC 140 PE10 TIOC3C NC 141 VS...

Page 75: ...hip PLL oscillator ground PLLCAP I PLL capacitance On chip PLL oscillator external capacitance connection pin EXTAL I External clock Connect a crystal oscillator Also an external clock can be input to the EXTAL pin XTAL I Crystal Connect a crystal oscillator CK O System clock Supplies the system clock to peripheral devices System control RES I Power on reset Power on reset when low MRES I Manual r...

Page 76: ... interrupt generation also during bus release Address bus A0 A21 O Address bus Outputs addresses Data bus D0 D15 QFP 112 D0 D31 QFP 144 I O Data bus 16 bit QFP 112 pin and TQFP 120 pin versions or 32 bit QFP 144 pin version bidirectional data bus Bus control CS0 CS3 O Chip selects 0 3 Chip select signals for external memory or devices RD O Read Indicates reading from an external device WRH O Upper...

Page 77: ...ming signal for DRAM column address strobe Output when bits 31 to 24 of data are accessed CASHL QFP 144 O HL column address strobe Timing signal for DRAM column address strobe Output when bits 23 to 16 of data are accessed Bus control multifunction timer pulse unit TCLKA TCLKB TCLKC TCLKD I MTU timer clock input Input pins for external clocks to the MTU counter TIOC0A TIOC0B TIOC0C TIOC0D I O MTU ...

Page 78: ...DACK0 DACK1 O DMA transfer strobe channels 0 1 Output a strobe to the external I O of external DMA transfer requests Serial communication interface SCI TxD0 TxD1 O Transmit data channels 0 1 SCI0 SCI1 transmit data output pins TxD1 is used for data transfer during boot mode of F ZTAT RxD0 RxD1 I Receive data channels 0 1 SCI0 SCI1 receive data input pins RxD1 is used for data transfer during boot ...

Page 79: ...O General purpose port General purpose input output port pins Each bit can be designated for input output PD0 PD15 QFP 112 PD0 PD31 QFP 144 I O General purpose port General purpose input output port pins Each bit can be designated for input output PE0 PE15 I O General purpose port General purpose input output port pins Each bit can be designated for input output PF0 PF7 I General purpose port Gene...

Page 80: ... is used for data transfer It is possible to automatically adjust the transfer bit rate to the transfer bit rate of the host Table 1 8 Pins during the Onboard Programming Mode Notation I O Function FWP Input Hardware protected flash memory write delete MD1 Input User programming mode boot mode setting MD2 Input Clock mode PLL setting MD3 Input Clock mode PLL setting TxD1 Output Serial sent data ou...

Page 81: ...st Write control program Write control program area Boot program area Application program Application program SH7044 45 RXD1 TXD1 Boot program Flash memory RAM SCI 1 Figure 1 7 Data Transfer during Boot Mode ...

Page 82: ...44 ...

Page 83: ...5 is used as the hardware stack pointer SP Saving and recovering the status register SR and program counter PC in exception processing is accomplished by referencing the stack using R15 Figure 2 1 shows the general registers R0 1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP hardware stack pointer 2 0 31 1 2 R0 functions as an index register in the indirect indexed register addressing mode...

Page 84: ...s bit always read 0 The write value should always be 0 Reserved bits 0 is read Write only Bits I0 I3 Interrupt mask bits M and Q bits Used by the DIV0U DIV0S and DIV1 instructions Global base register GBR Indicates the base address of the indirect GBR addressing mode The indirect GBR addressing mode is used in data transfer for on chip peripheral modules register areas and in logic operations Vect...

Page 85: ...and low MACH MACL Stores the results of multiply and accumulate operations Procedure register PR Stores a return address from a subroutine procedure Program counter PC Indicates the fourth byte second instruction after the current instruction Figure 2 3 System Registers 2 1 4 Initial Values of Registers Table 2 1 lists the values of the registers after reset Table 2 1 Initial Values of Registers C...

Page 86: ... cannot be guaranteed The hardware stack area referred to by the hardware stack pointer SP R15 uses only longword data starting from address 4n because this area holds the program counter and status register figure 2 5 31 0 15 23 7 Byte Byte Byte Byte Word Word Address 2n Address 4n Longword Address m Address m 2 Address m 1 Address m 3 Figure 2 5 Byte Word and Longword Alignment 2 2 3 Immediate D...

Page 87: ...e data is sign extended for arithmetic operations or zero extended for logic operations It also is handled as longword data table 2 2 Table 2 2 Sign Extension of Word Data SH7040 Series CPU Description Example of Conventional CPU MOV W disp PC R1 ADD R1 R0 DATA W H 1234 Data is sign extended to 32 bits and R1 becomes H 00001234 It is next operated upon by an ADD instruction ADD W H 1234 R0 Note di...

Page 88: ...condition true false that determines if the program will branch The number of instructions that change the T bit is kept to a minimum to improve the processing speed table 2 4 Table 2 4 T Bit SH7040 Series CPU Description Example of Conventional CPU CMP GE R1 R0 BT TRGET0 BF TRGET1 T bit is set when R0 R1 The program branches to TRGET0 when R0 R1 and to TRGET1 when R0 R1 CMP W R1 R0 BGE TRGET0 BLT...

Page 89: ...addressing mode table 2 6 Table 2 6 Absolute Address Accessing Classification SH7040 Series CPU Example of Conventional CPU Absolute address MOV L disp PC R1 MOV B R1 R0 DATA L H 12345678 MOV B H 12345678 R0 Note disp PC accesses the immediate data 16 Bit 32 Bit Displacement When data is accessed by 16 bit or 32 bit displacement the pre existing displacement value is placed in the memory table Loa...

Page 90: ...er addressing Rn The effective address is the content of register Rn A constant is added to the content of Rn after the instruction is executed 1 is added for a byte operation 2 for a word operation and 4 for a longword operation Rn Rn 1 2 4 Rn 1 2 4 Rn After the instruction executes Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Pre decrement indirect register addressing Rn The effective address is t...

Page 91: ...longword operation Rn Rn disp 1 2 4 1 2 4 disp zero extended Byte Rn disp Word Rn disp 2 Longword Rn disp 4 Indirect indexed register addressing R0 Rn The effective address is the Rn value plus R0 Rn R0 Rn R0 Rn R0 Indirect GBR addressing with displacement disp 8 GBR The effective address is the GBR value plus an 8 bit displacement disp The value of disp is zero extended and remains the same for a...

Page 92: ... GBR R0 PC relative addressing with displacement disp 8 PC The effective address is the PC value plus an 8 bit displacement disp The value of disp is zero extended and is doubled for a word operation and quadrupled for a longword operation For a longword operation the lowest two bits of the PC value are masked PC H FFFFFFFC PC disp 2 or PC H FFFFFFFC disp 4 2 4 for longword disp zero extended Word...

Page 93: ...e effective address is the PC value sign extended with a 12 bit displacement disp doubled and added to the PC value PC 2 disp sign extended PC disp 2 PC disp 2 Rn The effective address is the register PC value plus Rn PC Rn PC Rn PC Rn Immediate addressing imm 8 The 8 bit immediate data imm for the TST AND OR and XOR instructions are zero extended imm 8 The 8 bit immediate data imm for the MOV ADD...

Page 94: ...on Formats Source Operand Destination Operand Example 0 format xxxx xxxx xxxx xxxx 15 0 NOP n format nnnn Direct register MOVT Rn xxxx xxxx xxxx nnnn 15 0 Control register or system register nnnn Direct register STS MACH Rn Control register or system register nnnn Indirect pre decrement register STC L SR Rn m format mmmm Direct register Control register or system register LDC Rm SR xxxx mmmm xxxx ...

Page 95: ... Rm Rn mmmm Direct register nnnn Indirect pre decrement register MOV L Rm Rn mmmm Direct register nnnn Indirect indexed register MOV L Rm R0 Rn md format xxxx dddd 15 0 mmmm xxxx mmmmdddd indirect register with displacement R0 Direct register MOV B disp Rm R0 nd4 format xxxx xxxx dddd 15 0 nnnn R0 Direct register nnnndddd Indirect register with displacement MOV B R0 disp Rn nmd format nnnn xxxx dd...

Page 96: ...R0 Direct register MOVA disp PC R0 dddddddd PC relative BF label d12 format dddd xxxx 15 0 dddd dddd dddddddddddd PC relative BRA label label disp PC nd8 format dddd nnnn xxxx 15 0 dddd dddddddd PC relative with displacement nnnn Direct register MOV L disp PC Rn i format iiiiiiii Immediate Indirect indexed GBR AND B imm R0 GBR xxxx xxxx i i i i 15 0 i i i i iiiiiiii Immediate R0 Direct register AN...

Page 97: ...perations ADDC Binary addition with carry ADDV Binary addition with overflow check CMP cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division DMULS Signed double length multiplication DMULU Unsigned double length multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply accumulate double length multiply accumu...

Page 98: ... rotation with T bit SHAL One bit arithmetic left shift SHAR One bit arithmetic right shift SHLL One bit logical left shift SHLLn n bit logical left shift SHLR One bit logical right shift SHLRn n bit logical right shift Branch 9 BF Conditional branch conditional branch with delay Branch when T 0 11 BT Conditional branch conditional branch with delay Branch when T 1 BRA Unconditional branch BRAF Un...

Page 99: ...rol register LDS Load to system register NOP No operation RTE Return from exception processing SETT T bit set SLEEP Shift into power down mode STC Storing control register data STS Storing system register data TRAPA Trap exception handling Total 62 142 Table 2 11 shows the format used in tables 2 12 to 2 17 which list instruction codes operation and execution states in order by classification ...

Page 100: ...each bit Exclusive OR of each bit Logical NOT of each bit n n bit left shift n n bit right shift Execution cycles Value when no wait states are inserted 2 T bit Value of T bit after instruction is executed An em dash in the column means no change Notes 1 Depending on the operand size displacement is scaled 1 2 or 4 For details see the SH 1 SH 2 SH DSP Programming Manual 2 Instruction execution cyc...

Page 101: ...nsion Rn 1 MOV L Rm Rn 0110nnnnmmmm0010 Rm Rn 1 MOV B Rm Rn 0010nnnnmmmm0100 Rn 1 Rn Rm Rn 1 MOV W Rm Rn 0010nnnnmmmm0101 Rn 2 Rn Rm Rn 1 MOV L Rm Rn 0010nnnnmmmm0110 Rn 4 Rn Rm Rn 1 MOV B Rm Rn 0110nnnnmmmm0100 Rm Sign extension Rn Rm 1 Rm 1 MOV W Rm Rn 0110nnnnmmmm0101 Rm Sign extension Rn Rm 2 Rm 1 MOV L Rm Rn 0110nnnnmmmm0110 Rm Rn Rm 4 Rm 1 MOV B R0 disp Rn 10000000nnnndddd R0 disp Rn 1 MOV W...

Page 102: ...00000dddddddd R0 disp GBR 1 MOV W R0 disp GBR 11000001dddddddd R0 disp 2 GBR 1 MOV L R0 disp GBR 11000010dddddddd R0 disp 4 GBR 1 MOV B disp GBR R0 11000100dddddddd disp GBR Sign extension R0 1 MOV W disp GBR R0 11000101dddddddd disp 2 GBR Sign extension R0 1 MOV L disp GBR R0 11000110dddddddd disp 4 GBR R0 1 MOVA disp PC R0 11000111dddddddd disp 4 PC R0 1 MOVT Rn 0000nnnn00101001 T Rn 1 SWAP B Rm...

Page 103: ...signed data 1 T 1 Comparison result CMP GE Rm Rn 0011nnnnmmmm0011 If Rn Rm with signed data 1 T 1 Comparison result CMP HI Rm Rn 0011nnnnmmmm0110 If Rn Rm with unsigned data 1 T 1 Comparison result CMP GT Rm Rn 0011nnnnmmmm0111 If Rn Rm with signed data 1 T 1 Comparison result CMP PL Rn 0100nnnn00010101 If Rn 0 1 T 1 Comparison result CMP PZ Rn 0100nnnn00010001 If Rn 0 1 T 1 Comparison result CMP ...

Page 104: ...110nnnnmmmm1111 A word in Rm is sign extended Rn 1 EXTU B Rm Rn 0110nnnnmmmm1100 A byte in Rm is zero extended Rn 1 EXTU W Rm Rn 0110nnnnmmmm1101 A word in Rm is zero extended Rn 1 MAC L Rm Rn 0000nnnnmmmm1111 Signed operation of Rn Rm MAC MAC 32 32 64 bit 3 2 to 4 MAC W Rm Rn 0100nnnnmmmm1111 Signed operation of Rn Rm MAC MAC 16 16 64 64 bit 3 2 MUL L Rm Rn 0000nnnnmmmm0111 Rn Rm MACL 32 32 32 bi...

Page 105: ... Bit SUB Rm Rn 0011nnnnmmmm1000 Rn Rm Rn 1 SUBC Rm Rn 0011nnnnmmmm1010 Rn Rm T Rn Borrow T 1 Borrow SUBV Rm Rn 0011nnnnmmmm1011 Rn Rm Rn Underflow T 1 Overflow Note The normal minimum number of execution cycles The number in parentheses is the number of cycles when there is contention with following instructions ...

Page 106: ...R0 GBR 3 TAS B Rn 0100nnnn00011011 If Rn is 0 1 T 1 MSB of Rn 4 Test result TST Rm Rn 0010nnnnmmmm1000 Rn Rm if the result is 0 1 T 1 Test result TST imm R0 11001000iiiiiiii R0 imm if the result is 0 1 T 1 Test result TST B imm R0 GBR 11001100iiiiiiii R0 GBR imm if the result is 0 1 T 3 Test result XOR Rm Rn 0010nnnnmmmm1010 Rn Rm Rn 1 XOR imm R0 11001010iiiiiiii R0 imm R0 1 XOR B imm R0 GBR 11001...

Page 107: ...B ROTCR Rn 0100nnnn00100101 T Rn T 1 LSB SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB SHLL Rn 0100nnnn00000000 T Rn 0 1 MSB SHLR Rn 0100nnnn00000001 0 Rn T 1 LSB SHLL2 Rn 0100nnnn00001000 Rn 2 Rn 1 SHLR2 Rn 0100nnnn00001001 Rn 2 Rn 1 SHLL8 Rn 0100nnnn00011000 Rn 8 Rn 1 SHLR8 Rn 0100nnnn00011001 Rn 8 Rn 1 SHLL16 Rn 0100nnnn00101000 Rn 16 Rn 1 SHLR16 Rn 0100nnnn00101...

Page 108: ...1 BT S label 10001101dddddddd Delayed branch if T 1 disp 2 PC PC if T 0 nop 2 1 BRA label 1010dddddddddddd Delayed branch disp 2 PC PC 2 BRAF Rm 0000mmmm00100011 Delayed branch Rm PC PC 2 BSR label 1011dddddddddddd Delayed branch PC PR disp 2 PC PC 2 BSRF Rm 0000mmmm00000011 Delayed branch PC PR Rm PC PC 2 JMP Rm 0100mmmm00101011 Delayed branch Rm PC 2 JSR Rm 0100mmmm00001011 Delayed branch PC PR ...

Page 109: ...MACL 1 LDS Rm PR 0100mmmm00101010 Rm PR 1 LDS L Rm MACH 0100mmmm00000110 Rm MACH Rm 4 Rm 1 LDS L Rm MACL 0100mmmm00010110 Rm MACL Rm 4 Rm 1 LDS L Rm PR 0100mmmm00100110 Rm PR Rm 4 Rm 1 NOP 0000000000001001 No operation 1 RTE 0000000000101011 Delayed branch stack area PC SR 4 SETT 0000000000011000 1 T 1 1 SLEEP 0000000000011011 Sleep 3 STC SR Rn 0000nnnn00000010 SR Rn 1 STC GBR Rn 0000nnnn00010010 ...

Page 110: ...s before the chip enters sleep mode The execution cycles shown in the table are minimums The actual number of cycles may be increased when 1 contention occurs between instruction fetches and data access or 2 when the destination register of the load instruction memory register and the register used by the next instruction are the same 2 5 Processing States 2 5 1 State Transitions The CPU has five ...

Page 111: ...d for SLEEP instruction SBY bit set for SLEEP instruction From any state when RES 0 From any state when RES 1 and MRES 0 Reset states Power down state Bus request generated Bus request cleared Figure 2 6 Transitions between Processing States Reset State The CPU resets in the reset state When the RES pin level goes low a power on reset results When the RES pin is high and MRES is low a manual reset...

Page 112: ... There are two power down state modes sleep mode and standby mode Sleep Mode When standby bit SBY in the standby control register SBYCR is cleared to 0 and a SLEEP instruction executed the CPU moves from program execution state to sleep mode In the sleep mode the CPU halts and the contents of its internal registers and the data in on chip cache or on chip RAM is maintained The on chip peripheral m...

Page 113: ...ns Clock CPU On Chip Peripheral Modules CPU Registers On Chip Cache or On Chip RAM I O Port Pins Canceling Sleep Execute SLEEP instruction with SBY bit cleared to 0 in SBYCR Run Halt Run Held Held Held Interrupt DMA address error Power on reset Manual reset Stand by Execute SLEEP instruction with SBY bit set to 1 in SBYCR Halt Halt Halt and initialize Held Held Held or Hi Z select able NMI interru...

Page 114: ...76 ...

Page 115: ...e On Chip CS0 Area No FWP MD3 1 MD2 1 MD1 MD0 Name ROM 112 Pin 144 Pin 0 1 x x 0 0 MCU mode 0 Not Active 8 bit space 16 bit space 1 1 x x 0 1 MCU mode 1 Not Active 16 bit space 32 bit space 2 1 x x 1 0 MCU mode 2 Active 8 16 bit space 2 8 16 32 bit space 2 3 1 x x 1 1 Single chip mode Active 4 1 1 1 1 1 PROM mode 3 Active 0 x x 0 0 Boot mode 4 Active 8 16 bit space 2 8 16 32 bit space 2 0 x x 0 1 ...

Page 116: ... for the 112 pin version and 16 bit for the 144 pin version MCU Mode 1 CS0 area becomes an external memory space with 16 bit bus width for the 112 pin version and 32 bit for the 144 pin version MCU Mode 2 The on chip ROM becomes effective The bus width for the on chip ROM space is 32 bit Mode 3 single chip mode Any port can be used but external addresses can not be employed Mode 4 PROM mode On chi...

Page 117: ...Connects to a crystal oscillator or used for external clock input pin PLLCAP Input Connects to a capacitor for PLL circuit operation MD0 Input Designates operating mode through the level applied to this pin MD1 Input Designates operating mode through the level applied to this pin MD2 Input Designates clock mode through the level applied to this pin MD3 Input Designates clock mode through the level...

Page 118: ...80 ...

Page 119: ...XTAL MD2 MD3 Oscillator PLL circuit Clock mode control circuitry Prescaler Within the LSI φ φ 2 to φ 8192 Figure 4 1 Block Diagram of the Clock Pulse Generator 4 2 Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock 4 2 1 Connecting a Crystal Oscillator Circuit Configuration A crystal oscillator can be connected as shown in figure 4 2 Use the damping res...

Page 120: ...scillator Use a crystal oscillator with the characteristics listed in table 4 2 Co EXTAL CL L Rs XTAL Figure 4 3 Crystal Oscillator Equivalent Circuit Table 4 2 Crystal Oscillator Parameters Frequency MHz Parameter 4 8 10 Rs max Ω 120 80 60 Co max pF 7 7 7 4 2 2 External Clock Input Method Figure 4 4 shows an example of an external clock input connection In this case make the external clock high l...

Page 121: ...TIOC4C DACK0 AH PE15 TIOC4D DACK1 IRQOUT are set to high impedance regardless of PFC setting Even in standby mode these six pins become high impedance regardless of PFC setting These pins enter the normal state after standby mode is cancelled When abnormalities that halt the oscillator occur except in standby mode other LSI operations become undefined In this case LSI operations including these si...

Page 122: ... route any signal lines near the oscillator circuitry When designing the board place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins Figure 4 5 shows the precautions regarding oscillator block board settings Crossing of signal lines prohibited CL1 XTAL EXTAL CL2 Figure 4 5 Cautions for Oscillator Circuit System Board Design ...

Page 123: ... supply source and be sure to insert bypass capacitors CPB and CB close to the pins If VCC and PLLVCC are both 3 3 V 0 3 V it is recommended that Rp be set to 0 Ω 4 5 3 Spread Spectrum Clock Generator Usage Notes The following points should be borne in mind when using a spread spectrum clock generator as an external oscillator in order to reduce radiation noise Set the center frequency and the spr...

Page 124: ...86 ...

Page 125: ... NMI User break IRQ On chip peripheral modules Direct memory access controller DMAC Multifunction timer pulse unit MTU Serial communications interface SCI A D converter A D 3 Data transfer controller DTC Compare match timer CMT Watchdog timer WDT Bus state controller BSC Port output enable control section Instructions Trap instruction TRAPA instruction General illegal instructions undefined code I...

Page 126: ...ed branch instruction delay slot or of instructions that rewrite the PC When exception processing starts the CPU operates as follows 1 Exception processing triggered by reset The initial values of the program counter PC and stack pointer SP are fetched from the exception processing vector table PC and SP are respectively the H 00000000 and H 00000004 addresses for power on resets and the H 0000000...

Page 127: ... and vector table address offsets Table 5 4 shows how vector table addresses are calculated Table 5 3 Exception Processing Vector Table Exception Sources Vector Numbers Vector Table Address Offset Power on reset PC 0 H 00000000 H 00000003 SP 1 H 00000004 H 00000007 Manual reset PC 2 H 00000008 H 0000000B SP 3 H 0000000C H 0000000F General illegal instruction 4 H 00000010 H 00000013 Reserved by sys...

Page 128: ...table 6 3 Interrupt Exception Processing Vectors and Priorities Table 5 4 Calculating Exception Processing Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address vector table address offset vector number 4 Address errors interrupts instructions Vector table address VBR vector table address offset VBR vector number 4 Notes 1 VBR Vector base register 2 V...

Page 129: ... the stack pointer SP is fetched from the exception processing vector table 3 The vector base register VBR is cleared to H 00000000 and the interrupt mask bits I3 I0 of the status register SR are set to H F 1111 4 The values fetched from the exception processing vector table are set in the program counter PC and SP and the program begins executing Be certain to always perform power on reset proces...

Page 130: ...ress error occurs Instruction fetched from other than on chip peripheral module space None normal Instruction fetched from on chip peripheral module space Address error occurs Instruction fetched from external memory space when in single chip mode Address error occurs Data CPU or Word data accessed from even address None normal read write DMAC Word data accessed from odd address Address error occu...

Page 131: ...h 5 4 Interrupts Table 5 7 shows the sources that start up interrupt exception processing These are divided into NMI user breaks IRQ and on chip peripheral modules Table 5 7 Interrupt Sources Type Request Source Number of Sources NMI NMI pin external input 1 User break User break controller 1 IRQ IRQ0 IRQ7 external input 8 On chip peripheral module Direct memory access controller DMAC 4 Multifunct...

Page 132: ...ty level setting registers A through H IPRA IPRH On chip peripheral module 0 15 Set with interrupt priority level setting registers A through H IPRA IPRH 5 4 2 Interrupt Exception Processing When an interrupt occurs its priority level is ascertained by the interrupt controller INTC NMI is always accepted but other interrupts are only accepted if they have a priority level higher than the priority ...

Page 133: ...mber specified in the TRAPA instruction That address is jumped to and the program starts executing The jump that occurs is not a delayed branch 5 5 2 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot When the instruction placed in the delay slot is undefined code illegal slot exception processing starts up when that ...

Page 134: ...mmediately after a Delayed Branch Instruction or Interrupt Disabled Instruction Exception Source Point of Occurrence Address Error Interrupt Immediately after a delayed branch instruction 1 Not accepted Not accepted Immediately after an interrupt disabled instruction 2 Accepted Not accepted Notes 1 Delayed branch instructions JMP JSR BRA BSR RTS RTE BF S BT S BSRF BRAF 2 Interrupt disabled instruc...

Page 135: ...ror 32 bits 32 bits SR Address of instruction after executed instruction SP Trap instruction 32 bits 32 bits SR Address of instruction after TRAPA instruction SP General illegal instruction 32 bits 32 bits SR Start address of illegal instruction SP Interrupt 32 bits 32 bits SR Address of instruction after executed instruction SP Illegal slot instruction 32 bits 32 bits SR Jump destination address ...

Page 136: ...ption processing will start up as soon as the first exception processing is ended Address errors will then also occur in the stacking for this address error exception processing To ensure that address error exception processing does not go into an endless loop no address errors are accepted at that point This allows program control to be shifted to the address error exception service routine and e...

Page 137: ...egisters the priorities of IRQ interrupts and on chip peripheral module interrupts can be set in 16 levels for different request sources NMI noise canceler function NMI input level bits indicate the NMI pin status By reading these bits with the interrupt exception service routine the pin status can be confirmed enabling it to be used as a noise canceler Notification of interrupt occurrence can be ...

Page 138: ...MT SCI A D DTC Interrupt request Interrupt request Interrupt request WDT BSC I O UBC DMAC MTU CMT SCI A D DTC WDT BSC User break controller Direct memory access controller Multifunction timer pulse unit Compare match timer Serial communication interface A D converter Data transfer controller Watchdog timer Bus state controller DRAM refresh control section I O ICR ISR DTER IPRA IPRH SR I O port por...

Page 139: ...Name Abbr R W Initial Value Address Access Sizes Interrupt priority register A IPRA R W H 0000 H FFFF8348 8 16 32 Interrupt priority register B IPRB R W H 0000 H FFFF834A 8 16 32 Interrupt priority register C IPRC R W H 0000 H FFFF834C 8 16 32 Interrupt priority register D IPRD R W H 0000 H FFFF834E 8 16 32 Interrupt priority register E IPRE R W H 0000 H FFFF8350 8 16 32 Interrupt priority registe...

Page 140: ...nterrupts are requested by input from pins IRQ0 IRQ7 Set the IRQ sense select bits IRQ0S IRQ7S of the interrupt control register ICR to select low level detection or falling edge detection for each pin The priority level can be set from 0 to 15 for each pin using the interrupt priority registers A and B IPRA IPRB When IRQ interrupts are set to low level detection an interrupt request signal is sen...

Page 141: ...e 6 3 lists interrupt sources and their vector numbers vector table address offsets and interrupt priorities Each interrupt source is allocated a different vector number and vector table address offset Vector table addresses are calculated from vector numbers and address offsets In interrupt exception processing the exception service routine start address is fetched from the vector table indicated...

Page 142: ... 15 0 IPRA 15 12 IRQ1 65 H 00000104 H 00000107 0 15 0 IPRA 11 8 IRQ2 66 H 00000108 H 0000010B 0 15 0 IPRA 7 4 IRQ3 67 H 0000010C H 0000010F 0 15 0 IPRA 3 0 IRQ4 68 H 00000110 H 00000113 0 15 0 IPRB 15 12 IRQ5 69 H 00000114 H 00000117 0 15 0 IPRB 11 8 IRQ6 70 H 00000118 H 0000011B 0 15 0 IPRB 7 4 IRQ7 71 H 0000011C H 0000011F 0 15 0 IPRB 3 0 DMAC0 DEI0 72 H 00000120 H 00000123 0 15 0 IPRC 15 12 DMA...

Page 143: ...0000167 0 15 0 TGI0C 90 H 00000168 H 0000016B 0 15 0 TGI0D 91 H 0000016C H 0000016F 0 15 0 Low TCI0V 92 H 00000170 H 00000173 0 15 0 IPRD 11 8 MTU1 TGI1A 96 H 00000180 H 00000183 0 15 0 IPRD 7 4 High TGI1B 97 H 00000184 H 00000187 0 15 0 Low TCI1V 100 H 00000190 H 00000193 0 15 0 IPRD 3 0 High TCI1U 101 H 00000194 H 00000197 0 15 0 Low MTU2 TGI2A 104 H 000001A0 H 000001A3 0 15 0 IPRE 15 12 High TG...

Page 144: ...01C8 H 000001CB 0 15 0 TGI3D 115 H 000001CC H 000001CF 0 15 0 Low TCI3V 116 H 000001D0 H 000001D3 0 15 0 IPRE 3 0 MTU4 TGI4A 120 H 000001E0 H 000001E3 0 15 0 IPRF 15 12 High TGI4B 121 H 000001E4 H 000001E7 0 15 0 TGI4C 122 H 000001E8 H 000001EB 0 15 0 TGI4D 123 H 000001EC H 000001EF 0 15 0 Low TCI4V 124 H 000001F0 H 000001F3 0 15 0 IPRF 11 8 High Reserved 125 H 000001F4 H 000001F7 0 15 0 Low SCI0 ...

Page 145: ...18 H 0000021B 0 15 0 TEI1 135 H 0000021C H 0000021F 0 15 0 Low A D ADI 136 H 00000220 H 00000223 0 15 0 IPRG 15 12 DTC SWDTCE 140 H 00000230 H 00000233 0 15 0 IPRG 11 8 CMT0 CMI0 144 H 00000240 H 00000243 0 15 0 IPRG 7 4 CMT1 CMI1 148 H 00000250 H 00000253 0 15 0 IPRG 3 0 WDT ITI 152 H 00000260 H 00000263 0 15 0 IPRH 15 12 High BSC CMI 153 H 00000264 H 00000267 0 15 0 Low I O OEI 156 H 00000270 H ...

Page 146: ... 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table 6 4 Interrupt Request Sources and IPRA IPRH Bits Register 15 12 11 8 7 4 3 0 Interrupt priority register A IRQ0 IRQ1 IRQ2 IRQ3 Interrupt priority register B IRQ4 IRQ5 IRQ6 IRQ7 Interrupt priority register C DMAC0 DMAC1 DMAC2 DMAC3 Interrupt priority register D MTU0 MTU0 MTU1 MTU1 Interrupt priority register E ...

Page 147: ...l Register ICR The ICR is a 16 bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 IRQ7 and indicates the input signal level to the NMI pin A power on reset initializes ICR but the standby mode does not Bit 15 14 13 12 11 10 9 8 NMIL NMIE Initial value 0 0 0 0 0 0 0 R W R R R R R R R R W Bit 7 6 5 4 3 2 1 0 IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ...

Page 148: ... IRQ input 6 3 3 IRQ Status Register ISR The ISR is a 16 bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 IRQ7 When IRQ interrupts are set to edge detection held interrupt requests can be withdrawn by writing a 0 to IRQnF after reading an IRQnF 1 A power on reset initializes ISR but the standby mode does not Bit 15 14 13 12 11 10 9 8 Initial value ...

Page 149: ...Qn interrupt exception processing has been executed 3 When a DTC transfer due to IRQn interrupt has been executed 1 Level detection An IRQn interrupt request exists Set conditions When IRQn input is low level Edge detection An IRQn interrupt request was detected Set conditions When a falling edge occurs at an IRQn input IRQ pin Edge detection Selection CPU interrupt request DTC activation request ...

Page 150: ...is equal to or less than the level set in I3 I0 the request is ignored If the request priority level is higher than the level in bits I3 I0 the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU 4 When the interrupt controller accepts an interrupt a low level is output from the IRQOUT pin 5 The CPU detects the interrupt request sent from the interrupt contr...

Page 151: ...ion vector table Notes 1 2 IRQOUT is the same signal as the interrupt request signal to the CPU see figure 6 1 Thus it is output when there is a higher priority interrupt request than the one in the I3 to I0 bits of the SR When the accepted interrupt is sensed by edge the IRQOUT pin becomes high level at the point when the CPU starts interrupt exception processing instead of instruction execution ...

Page 152: ...r the executing instruction Always be certain that SP is a multiple of 4 Figure 6 4 Stack after Interrupt Exception Processing 6 5 Interrupt Response Time Table 6 5 indicates the interrupt response time which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins Figure 6 ...

Page 153: ...masking instruction follows however the time may be even longer Time from start of interrupt exception processing until fetch of first instruction of exception service routine starts 5 m1 m2 m3 Performs the PC and SR saves and vector address fetch Interrupt Total 7 m1 m2 m3 9 m1 m2 m3 response Minimum 10 12 0 35 0 42 µs at 28 7 MHz time Maximum 12 2 m1 m2 m3 m4 13 2 m1 m2 m3 m4 0 67 0 70 µs at 28 ...

Page 154: ...t Signals The following data transfers can be done using interrupt request signals Activate DMAC only without generating CPU interrupt Activate DTC only CPU interrupts according to DTC settings Among interrupt sources those designated as DMAC activating sources are masked and not input to the INTC The masking condition is listed below Mask condition DME DE0 source selection 0 DE1 source selection ...

Page 155: ... or clear the DME bit to 0 2 For DTC set the corresponding DTE bits and DISEL bits to 1 3 Activating sources are applied to the DTC when interrupts occur 4 When the DTC performs a data transfer it clears the DTE bit to 0 and sends an interrupt request to the CPU The activating source does not clear 5 The CPU clears interrupt sources with its interrupt processing routine It then confirms the transf...

Page 156: ...o 1 and clear the DISEL bits to 0 3 Activating sources are applied to the DTC when interrupts occur 4 When the DTC performs a data transfer it clears the activating source An interrupt request is not sent to the CPU because the DTE bit is maintained as a 1 5 However when the transfer counter value 0 the DTE bit is cleared to 0 and an interrupt request is sent to the CPU 6 The CPU performs the nece...

Page 157: ...to easily debug programs without using a large in circuit emulator 7 1 1 Features The features of the user break controller are Break compare conditions can be set Address CPU cycle or DMA DTC cycle Instruction fetch or data access Read or write Operand size byte word longword User break interrupt generated upon satisfying break conditions A user designed user break interrupt exception processing ...

Page 158: ...ak interrupt generating circuit UBC UBARH UBARL UBAMRH UBAMRL UBBR User break address registers H L User break address mask registers H L User break bus cycle register Figure 7 1 User Break Controller Block Diagram 7 1 3 Register Configuration The UBC has the five registers shown in table 7 1 Break conditions are established using these registers ...

Page 159: ...k address register UBAR consists of user break address register H UBARH and user break address register L UBARL Both are 16 bit readable writable registers UBARH stores the upper bits bits 31 16 of the address of the break condition while UBARL stores the lower bits bits 15 0 Resets and hardware standbys initialize both UBARH and UBARL to H 0000 They are not initialized in manual reset or software...

Page 160: ...AMR The user break address mask register UBAMR consists of user break address mask register H UBAMRH and user break address mask register L UBAMRL Both are 16 bit readable writable registers UBAMRH designates whether to mask any of the break address bits established in the UBARH and UBAMRL designates whether to mask any of the break address bits established in the UBARL Resets and hardware standby...

Page 161: ...ress Mask 15 0 UBM15 UBM0 These bits designate whether to mask any of the break address 15 0 bits UBA15 UBA0 established in the UBARL Bits 15 0 UBMn Description 0 Break address UBAn is included in the break conditions initial value 1 Break address UBAn is not included in the break conditions Note n 31 0 7 2 3 User Break Bus Cycle Register UBBR User break bus cycle register UBBR is a 16 bit readabl...

Page 162: ... for CPU cycles or peripheral cycles DMA DTC cycles Bit 7 CP1 Bit 6 CP0 Description 0 0 No user break interrupt occurs initial value 1 Break on CPU cycles 1 0 Break on peripheral cycles 1 Break on both CPU and peripheral cycles Bits 5 and 4 Instruction Fetch Data Access Select ID1 ID0 These bits select whether to break on instruction fetch and or data access cycles Bit 5 ID1 Bit 4 ID0 Description ...

Page 163: ...1 SZ1 Bit 0 SZ0 Description 0 0 Operand size is not a break condition initial value 1 Break on byte access 1 0 Break on word access 1 Break on longword access Note When breaking on an instruction fetch set the SZ0 bit to 0 All instructions are considered to be word size accesses even when there are instructions in on chip memory and 2 instruction fetches are done simultaneously in 1 bus cycle Oper...

Page 164: ... When the set conditions are satisfied the UBC sends a user break interrupt request signal to the interrupt controller INTC 3 The interrupt controller checks the accepted user break interrupt request signal s priority level The user break interrupt has priority level 15 so it is accepted only if the interrupt mask level in bits I3 I0 in the status register SR is 14 or lower When the I3 I0 bit leve...

Page 165: ...W0 ID1 ID0 CP1 CP0 UBARH UBARL UBAMRH UBAMRL 32 32 32 32 32 Internal address bits 31 0 CPU cycle DMA DTC cycle Instruction fetch Data access Read cycle Write cycle Byte size Word size Longword size Figure 7 2 Break Condition Judgment Method ...

Page 166: ...the user break interrupt is not accepted immediately but the break condition establishing instruction is executed The user break interrupt is accepted after execution of the instruction that has accepted the interrupt In this case the PC value saved is the start address of the instruction that will be executed after the instruction that has accepted the interrupt Break on Data Access CPU Periphera...

Page 167: ...h was performed for an even address However if the first instruction fetch address after the branch is an odd address set by these conditions user break interrupt exception processing will be done after address error exception processing 7 4 2 Break on CPU Data Access Cycle 1 Register settings UBARH H 0012 UBARL H 3456 UBBR H 006A Conditions set Address H 00123456 Bus cycle CPU data access write w...

Page 168: ...ions but the contents of the UBC break condition registers are changed so as to alter the break condition immediately after the first of the two instructions is fetched a user break interrupt will still occur when the second instruction is fetched 7 5 2 Instruction Fetch at Branches When a conditional branch instruction or TRAPA instruction causes a branch instructions are fetched and executed as ...

Page 169: ... between User Break and Exception Handling If a user break is set for the fetch of a particular instruction and exception handling with higher priority than a user break is in contention and is accepted in the decode stage for that instruction or the next instruction user break exception handling may not be performed after completion of the higher priority exception handling routine on return by R...

Page 170: ...132 ...

Page 171: ... designated for both transfer source and destination Transfer devices Memory On chip ROM on chip RAM external ROM external RAM On chip peripheral modules excluding DMAC DTC Memory mapped external devices Abundant transfer modes Can select between normal mode repeat mode block transfer mode Can select between increment decrement fixed for source destination address Transfer units can be set as byte...

Page 172: ...Bus controller Register control Activation control Request priority control Bus interface DTC module bus DTMR DTCR DTSAR DTDAR DTIAR DTER DTCSR DTBR Internal bus DTMR DTCR DTSAR DTDAR DTC mode register DTC count register DTC source address register DTC destination address register DTIAR DTER DTCSR DTBR DTC initial address register DTC enable register DTC control status register DTC information bas...

Page 173: ...ster B DTCRB 2 Undefined 2 2 DTC enable register A DTEA R W H 00 H FFFF8700 8 16 32 DTC enable register B DTEB R W H 00 H FFFF8701 8 16 32 DTC enable register C DTEC R W H 00 H FFFF8702 8 16 32 DTC enable register D DTED R W H 00 H FFFF8703 8 16 32 DTC enable register E DTEE R W H 00 H FFFF8704 8 16 32 DTC control status register DTCSR R W 3 H 0000 H FFFF8706 8 16 32 DTC information base register ...

Page 174: ...ixed 1 0 DTSAR is incremented after transfer 1 for byte unit transfer 2 for word 4 for longword 1 1 DTSAR is decremented after transfer 1 for byte unit transfer 2 for word 4 for longword Bits 13 12 Destination Address Mode 1 0 DM1 DM0 These bits designate whether to hold increment or decrement the DTDAR after a data transfer Bit 13 DM1 Bit 12 DM0 Description 0 DTDAR remains fixed 1 0 DTDAR is incr...

Page 175: ...repeat mode or block transfer mode this bit designates whether the source side or destination side will be the repeat area or block area Bit 7 DTS Description 0 Destination side is the repeat area or block area 1 Source side is the repeat area or block area Bit 6 DTC Chain Enable CHNE This bit designates whether to perform continuous DTC data transfers with the same activating source Continued tra...

Page 176: ...ansfer upon an NMI 1 Continue DTC transfer until end of transfer being executed Bits 3 0 Reserved They have no effect on DTC operation 8 2 2 DTC Source Address Register DTSAR The DTC source address register DTSAR is a 32 bit register that specifies the DTC transfer source address An even address indicates that the transfer size is word a multiple of four address means it is longword The contents o...

Page 177: ... Note Initial value is undefined 8 2 5 DTC Transfer Count Register A DTCRA DTCRA is a 16 bit register that specifies the number of DTC transfers The contents of this register are located in memory In normal mode it functions as a 16 bit transfer counter The number of transfers is 1 when the set value is H 0001 65535 when it is H FFFF and 65536 when it is H 0000 In repeat mode DTCRAH maintains the ...

Page 178: ...3 12 11 10 9 8 Initial value R W Bit 7 6 5 4 3 2 1 0 Initial value R W Note Initial value is undefined 8 2 7 DTC Enable Registers DTER The DTER DTEA DTEE are five 8 bit readable writable registers with bits allocated to each interrupt source that activates the DTC They set disable enable for DTC activation for each interrupt source When a bit is 1 DTC activation by the corresponding interrupt sour...

Page 179: ...ion It also indicates the DTC transfer status The DTCSR is initialized to H 0000 by power on resets and in standby mode Manual reset does not initialize DTCSR Bit 15 14 13 12 11 10 9 8 NMIF AE SWDTE Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W 1 R W 1 R W 2 Bit 7 6 5 4 3 2 1 0 Bit name DTVEC7 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value 0 0 0 0 0 0 0 0 R W R W 3 R W 3 R W 3 R ...

Page 180: ...ed even if the DTER bit is set to 1 To clear the AE bit read the 1 from it then write a 0 The AE bit is initialized to 0 by power on resets and in standby mode Bit 9 AE Description 0 No address error by the DTC initial value Clear condition Write a 0 after reading the AE bit 1 An address error by the DTC occurred Bit 8 DTC Software Activation Enable Bit SWDTE This bit enables disables DTC activati...

Page 181: ...ndefined 8 3 Operation The DTC stores transfer information in memory When there are DTC transfer requests it reads that transfer information and performs data transfers based on it It rewrites the transfer information to memory after data transfers Storing transfer information in memory makes it possible to perform data transfers for an arbitrary number of channels Further setting the CHNE bit to ...

Page 182: ...k transfer mode DTCRAL DTCRAL 1 repeat mode DTSAR DTDAR update DTCRB DTCRB 1 block transfer mode Transfer 1 transfer unit Block transfer mode and DTCRB 0 Transfer information write NMI or address error End Transfer information write CHNE 0 NMIF NMIM AE 1 When DISEL 1 or DTCRA 0 normal block transfer mode When DISEL 1 repeat transfer mode CPU interrupt request Figure 8 2 DTC Operation Flowchart ...

Page 183: ...DTCE interrupt is requested of the CPU the SWDTE bit of the DTCSR is automatically cleared When a request is made of the CPU the SWDTE bit is maintained as a 1 When multiple DTC activating sources occur simultaneously they are accepted and the DTC is activated in accordance with the default priority rankings shown in table 8 2 Figure 8 3 shows a block diagram of activating source control IRQ On ch...

Page 184: ... register information start address Always designate register information start addresses in multiples of four Register information start address DTBR upper 16 bits Memory space DTC vector table Register information DTC vector address Register information start address lower 16 bits Figure 8 4 Correspondence between DTC Vector Address and Register Information ...

Page 185: ...00417 DTEB4 Arbitrary 1 Arbitrary 1 CH1 TGI1B H 00000418 H 00000419 DTEB3 Arbitrary 1 Arbitrary 1 MTU TGI0A H 0000041A H 0000041B DTEB2 Arbitrary 1 Arbitrary 1 CH0 TGI0B H 0000041C H 0000041D DTEB1 Arbitrary 1 Arbitrary 1 TGI0C H 0000041E H 0000041F DTEB0 Arbitrary 1 Arbitrary 1 TGI0D H 00000420 H 00000421 DTEC7 Arbitrary 1 Arbitrary 1 A D ADI ADI0 2 H 00000422 H 00000423 DTEC6 ADDR Arbitrary 1 IR...

Page 186: ...ternal devices on chip memory on chip peripheral modules excluding DMAC and DTC 2 Excluding A mask products are ADI A mask products are ADI0 8 3 4 Register Information Placement Figure 8 5 shows the placement of register information in memory space The register information start addresses are designated by DTBR for the upper 16 bits and the DTC vector table for the lower 16 bits The placement in o...

Page 187: ...ransfers of a number of bytes specified by the SCI are possible Table 8 3 shows the register functions for normal mode Table 8 3 Normal Mode Register Functions Values Written Back upon a Transfer Information Write Register Function When DTCRA is other than 1 When DTCRA is 1 DTMR Operation mode control DTMR DTMR DTCRA Transfer count DTCRA 1 DTCRA 1 H 0000 DTSAR Transfer source address Increment dec...

Page 188: ...t DTCRAL 1 DTCRAH DTIAR Initial address Not written back Not written back DTSAR Transfer source address Increment decrement fixed DTS 0 Increment decrement fixed DTS 1 DTIAR DTDAR Transfer destination address Increment decrement fixed DTS 0 DTIAR DTS 1 Increment decrement fixed 8 3 7 Block Transfer Mode Performs the transfer of one block for each one activation Either the transfer source or transf...

Page 189: ... 1 Increment decrement fixed 8 3 8 Operation Timing Figure 8 6 shows a DTC operation timing example Activating source DTC request Address Vector read Data transfer Transfer information read Transfer information write R W φ Figure 8 6 DTC Operation Timing Example Normal Mode When register information is located in on chip RAM each mode requires 4 cycles for transfer information reads and 3 cycles f...

Page 190: ... 3 2 2 2 2 Execution Vector read SI 1 4 2 2 state Register information read write SJ 1 1 8 4 2 Byte data read SK 1 1 2 3 2 2 2 Word data read SK 1 1 2 3 4 2 2 Long word data read SK 1 1 4 6 8 4 2 Byte data write SL 1 1 2 3 2 2 2 Word data write SL 1 1 2 3 4 2 2 Long word write SL 1 1 4 6 8 4 2 Internal operation SM 1 Notes 1 Two state access module port INT CMT SCI etc 2 Three state access module ...

Page 191: ... the DTCSR is 0 When the SWDTE bit is 1 the DTC is already being driven by software 4 Write a 1 to the SWDTE bit and a vector number to the DTVEC byte data 5 When SWDTCE interrupt requests are not made to the CPU the SWDTE bit is cleared When interrupts are requested the SWDTE bit is maintained as a 1 6 The SWDTE bit is cleared to 0 within the CPU interrupt routine For continuous DTC data transfer...

Page 192: ... processing routine clears the RDRF and performs the other completion processing 8 4 Cautions on Use DMAC and DTC register access by the DTC is prohibited DTC register access by the DMAC is prohibited When setting a bit in DTER first ensure that all transfers on the DTC channel corresponding to that DTER have ended or disable the transfer source for each channel so that DTC transfer corresponding ...

Page 193: ...e tag and cache data configuration is shown in figure 9 1 1 kbyte capacity External memory CS space and DRAM space instruction code and PC relative data caching 256 entry cache tag tag address 15 bits 4 byte line length Direct map replacement algorithm Valid flag 1 bit included for purges Cache tag 256 entries Data 32 bits Tag address 15 bits Cache data Data bus Hit signal CPU address Tag address ...

Page 194: ...oller Cache data Internal address bus Internal data bus Bus state controller External bus interface CCR Cache Figure 9 2 Cache Block Diagram 9 1 3 Register Configuration The cache has one register which can be used to control the enabling or disabling of each cache space The register configuration is shown in table 9 1 ...

Page 195: ...esets but is not initialized by manual resets or standby mode Bit 15 14 13 12 11 10 9 8 Initial value R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 CE DRAM CE CS3 CE CS2 CE CS1 CE CS0 Initial value 0 0 0 0 0 R W R R R R W R W R W R W R W Note Bits 15 5 are undefined Bits 15 5 Reserved Reading these bits gives undefined values The write value should always be 0 Bit 4 DRAM Space Cache Enable CEDRAM Select...

Page 196: ...ct enable or to exclude it disable A 0 disables and a 1 enables such use Bit 1 CECS1 Description 0 CS1 space cache disabled initial value 1 CS1 space cache enabled Bit 0 CS0 Space Cache Enable CECS0 Selects whether to use CS0 space as a cache object enable or to exclude it disable A 0 disables and a 1 enables such use Bit 0 CECS0 Description 0 CS0 space cache disabled initial value 1 CS0 space cac...

Page 197: ...9 3 Cache Address Array Address Array Read Designates entry address and reads out the corresponding tag address value valid bit value Address Array Write Designates entry address and writes the designated tag address value valid bit value 9 3 2 Cache Data Array Read Write Space The cache data array has a compulsory read write figure 9 4 Address Upper 22 bits of the data array space address 22 bits...

Page 198: ...y 9 4 3 Cache Miss Penalty and Cache Fill Timing When a cache miss occurs a single idle cycle is generated as a penalty immediately before the cache fill access from external memory in the event of a cache miss as shown in figure 9 5 However in the case of consecutive cache misses idle cycles are not generated for the second and subsequent cache misses as shown in figure 9 6 As the timing for a ca...

Page 199: ... Figure 9 5 Cache Fill Timing in Case of Non Consecutive Cache Miss from Normal Space No Wait No CS Assert Extension Miss hit CK Internal address Address CSn RD Data CS assert additional extension Figure 9 6 Cache Fill Timing in Case of Consecutive Cache Misses from Normal Space No Wait CS Assert Extension ...

Page 200: ...OLUMN CS space Wait COLUMN RAS assert extension CK Internal address Address RAS CASxx Data DRAM access CS space access DRAM access Miss hit Figure 9 8 Cache Fill Timing in Case of Consecutive Cache Misses from DRAM Space RAS Down Mode TPC 0 RCD 0 No Wait 9 4 4 Cache Hit after Cache Miss The first cache hit after a cache miss is regarded as a cache miss and a cache fill without idle cycle generatio...

Page 201: ...ated space Bus width can be selected for each space 8 16 or 32 bits Wait states can be inserted by software for each space Wait states can be inserted via the WAIT pin in external memory spce accesses Outputs control signals for each space according to the type of memory connected On chip ROM and RAM interfaces On chip RAM access of 32 bits in 1 state On chip ROM access of 32 bits in 1 state Direc...

Page 202: ...Module bus CS0 to CS3 AH RDWR Wait control unit Memory control unit Peripheral bus WRHH WRHL WRH WRL CASHH CASHL CASH CASL RAS BSC WCR1 WCR2 BCR1 BCR2 Wait control register 1 Wait control register 2 Bus control register 1 Bus control register 2 DCR RTCNT RTCOR RTSCR DRAM area control register Refresh timer counter Refresh timer constant register Refresh timer control status register Figure 10 1 BS...

Page 203: ...g DRAM access WRH O Strobe that indicates a write cycle to the 3rd byte D15 D8 for ordinary space multiplex I O Also output during DRAM access WRL O Strobe that indicates a write cycle to the least significant byte D7 D0 for ordinary space multiplex I O Also output during DRAM access RDWR O Strobe indicating a write cycle to DRAM used for DRAM space RAS O RAS signal for DRAM used for DRAM space CA...

Page 204: ...l reset Values are maintained in standby mode Table 10 2 Register Configuration Name Abbr R W Initial Value Address Access Size Bus control register 1 BCR1 R W H 200F H FFFF8620 8 16 32 Bus control register 2 BCR2 R W H FFFF H FFFF8622 8 16 32 Wait state control register 1 WCR1 R W H FFFF H FFFF8624 8 16 32 Wait state control register 2 WCR2 R W H 000F H FFFF8626 8 16 32 DRAM area control register...

Page 205: ...n chip peripheral module space or on chip RAM space when 11111111 H FF CS space selection Decoded outputs CS0 to CS3 when A31 to A24 00000000 A0 Figure 10 2 Address Format This LSI uses 32 bit addresses A31 A24 are used to select the type of space and are not output externally Bits A23 and A22 are decoded and output as chip select signals CS0 CS3 for the corresponding areas when bits A31 A24 are 0...

Page 206: ...tes 8 16 32 bits 2 H 02000000 H FFFF7FFF Reserved Reserved H FFFF8000 H FFFF87FF On chip peripheral module On chip peripheral module 2 kbytes 8 16 bits H FFFF8800 H FFFFEFFF Reserved Reserved H FFFFF000 H FFFFFFFF On chip RAM On chip RAM 4 kbytes 32 bits Notes Do not access reserved spaces Operation cannot be guaranteed if they are accessed 1 With the 64 kbyte version of on chip ROM the ROM addres...

Page 207: ...ipheral modules are unavailable 1 Selected by the mode pin 8 16 bit when 112 pin and 120 pin 16 32 bit when 144 pin 2 Selected by on chip register settings 3 Ordinary space selected by on chip register settings Multiplex I O space 8 16 bit selected by the A14 bit 10 2 Description of Registers 10 2 1 Bus Control Register 1 BCR1 BCR1 is a 16 bit read write register that enables access to the MTU con...

Page 208: ...cts the use of CS3 space as ordinary space or address data multiplex I O space A 0 selects ordinary space and a 1 selects address data multiplex I O space When address data multiplex I O space is selected the address and data are multiplexed and output from the data bus When CS3 space is an address data multiplex I O space bus size is decided by the A14 bit A14 0 8 bit A14 1 16 bit Bit 8 IOE Descr...

Page 209: ... chip ROM effective mode When in on chip ROM ineffective mode the CS0 space bus size is specified by the mode pin Bit 3 CS3 Space Size Specification A3SZ Specifies the CS3 space bus size when A3LG 0 This is effective only when CS3 space is ordinary space When CS3 space is an address data multiplex I O space bus size is decided by the A14 bit Bit 3 A3SZ Description 0 Byte 8 bit size 1 Word 16 bit s...

Page 210: ...e the CS0 space bus size is specified by the mode pin However even in on chip ROM effective mode this bit is ignored when A0LG 1 CS0 space bus size becomes longword 32 bit 10 2 2 Bus Control Register 2 BCR2 BCR2 is a 16 bit read write register that specifies the number of idle cycles and CS signal assert extension of each CS space BCR2 is initialized by power on resets to H FFFF but is not initial...

Page 211: ...s IW31 IW30 specify the idle between cycles for CS3 space IW21 IW20 specify the idle between cycles for CS2 space IW11 IW10 specify the idle between cycles for CS1 space and IW01 IW00 specify the idle between cycles for CS0 space Bit 15 IW31 Bit 14 IW30 Description 0 0 No idle cycle after accessing CS3 space 1 Inserts one idle cycle after accessing CS3 space 1 0 Inserts two idle cycles after acces...

Page 212: ...0 6 Waits between Access Cycles for details CW3 specifies the continuous access idles for CS3 space CW2 specifies the continuous access idles for CS2 space CW1 specifies the continuous access idles for CS1 space and CW0 specifies the continuous access idles for CS0 space Bit 7 CW3 Description 0 No CS3 space continuous access idle cycles 1 One CS3 space continuous access idle cycle initial value Bi...

Page 213: ...pace access SW1 specifies the CS assert extension for CS1 space access and SW0 specifies the CS assert extension for CS0 space access Bit 3 SW3 Description 0 No CS3 space CS assert extension 1 CS3 space CS assert extension initial value Bit 2 SW2 Description 0 No CS2 space CS assert extension 1 CS2 space CS assert extension initial value Bit 1 SW1 Description 0 No CS1 space CS assert extension 1 C...

Page 214: ...ts for CS3 space access Bit 15 W33 Bit 14 W32 Bit 13 W31 Bit 12 W30 Description 0 0 0 0 No wait external wait input disabled 0 0 0 1 1 wait external wait input enabled 1 1 1 1 15 wait external wait input enabled initial value Bits 11 8 CS2 Space Wait Specification W23 W22 W21 W20 Specifies the number of waits for CS2 space access Bit 11 W23 Bit 10 W22 Bit 9 W21 Bit 8 W20 Description 0 0 0 0 No wai...

Page 215: ...it external wait input disabled 0 0 0 1 1 wait external wait input enabled 1 1 1 1 15 wait external wait input enabled initial value 10 2 4 Wait Control Register 2 WCR2 WCR2 is a 16 bit read write register that specifies the number of access cycles for DRAM space and CS space for DMA single address mode transfers Do not perform any DMA single address transfers before WCR2 is set WCR2 is initialize...

Page 216: ... Access Wait Specification DSW3 DSW2 DSW1 DSW0 Specifies the number of waits for CS space access 0 15 during DMA single address mode accesses These bits are independent of the W bits of the WCR1 Bit 3 DSW3 Bit 2 DSW2 Bit 1 DSW1 Bit 0 DSW0 Description 0 0 0 0 No wait external wait input disabled 0 0 0 1 1 wait external wait input enabled 1 1 1 1 15 wait external wait input enabled initial value 10 ...

Page 217: ...number of cycles after RAS is negated before next assert Bit 15 TPC Description 0 1 5 cycles initial value 1 2 5 cycles Bit 14 RAS CAS Delay Cycle Count RCD Specifies the number of row address output cycles Bit 14 RCD Description 0 1 cycle initial value 1 2 cycles Bits 13 12 CAS Before RAS Refresh RAS Assert Cycle Count TRAS1 TRAS0 Specify the number of RAS assert cycles for CAS before RAS refresh...

Page 218: ...ue 1 3 cycle 1 wait external wait disabled 1 0 4 cycle 2 wait external wait enabled 1 5 cycle 3 wait external wait enabled Bit 7 DRAM Idle Cycle Count DIW Specifies whether to insert idle cycles either when accessing a different external space CS space or when doing a DRAM write after DRAM reads Bit 7 DIW Description 0 No idle cycles initial value 1 1 idle cycle Bit 6 Reserved This bit always read...

Page 219: ...Status Register RTCSR RTCSR is a 16 bit read write register that selects the refresh mode and the clock input to the refresh timer counter RTCNT and controls compare match interrupts CMI RTCSR is initialized by power on resets and hardware standbys to H 0000 but is not initialized by manual resets or software standbys Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit ...

Page 220: ...ount up RTCNT and RTCOR match as both are H 0000 but in this case CMF is not set Bit 5 Compare Match Interrupt Enable CMIE Enables or disables an interrupt request caused by the CMF bit of the RTCSR when CMF is set to 1 Bit 5 CMIE Description 0 Disables an interrupt request caused by CMF initial value 1 Enables an interrupt request caused by CMF Bits 4 2 Clock Select CKS2 CKS0 Select the clock to ...

Page 221: ... RTCNT is a 16 bit read write register that is used as an 8 bit up counter for refreshes or generating interrupt requests RTCNT counts up with the clock selected by the CKS2 CKS0 bits of the RTCSR RTCNT values can always be read written by the CPU When RTCNT matches RTCOR RTCNT is cleared to H 0000 and the CMF flag of the RTCSR is set to 1 If the RFSH bit of RTCSR is 1 and the RMD bit is 0 at this...

Page 222: ...erformed If the refresh request is not processed before the next match the previous request becomes ineffective When the CMIE bit of the RTSCR is set to 1 an interrupt request is sent to the interrupt controller by this match signal The interrupt request is output continuously until the CMF bit of the RTSCR is cleared Bits 15 8 are reserved and cannot be used in setting the period They always read...

Page 223: ...s are performed in 2 states T1 CK Address CSn RD Read Write Data WRx Data T2 Figure 10 3 Basic Timing of Ordinary Space Access During a read irrespective of operand size all bits in the data bus width for the access space address are fetched by the LSI on RD using the required byte locations During a write the following signals are associated with transfer of these actual byte locations WRHH bits ...

Page 224: ...umber of wait states inserted into ordinary space access states can be controlled using the WCR settings figure 10 4 T1 TW CK Read Write Address CSn RD Data WRx Data T2 Figure 10 4 Wait Timing of Ordinary Space Access Software Wait Only ...

Page 225: ...0 5 shows the WAIT signal sampling The WAIT signal is sampled at the clock rise one cycle before the clock rise when Tw state shifts to T2 state T1 TW CK Read Write Address CSn WAIT RD Data WRx Data TW TW0 T2 Figure 10 5 Wait State Timing of Ordinary Space Access Wait States from Software Wait 2 State WAIT Signal ...

Page 226: ...interfaces with external circuitry The timing is shown in figure 10 6 Th and Tf cycles are added respectively before and after the ordinary cycle Only CSn is asserted in these cycles RD and WRx signals are not Further data is extended up to the Tf cycle which is effective for gate arrays and the like which have slower write operations Th T1 CK Read Write Address CSn RD Data WRx Data T2 Tf DACK Fig...

Page 227: ...be selected as from 9 to 12 bits by setting the AMX1 and AMX0 bits of the DCR Table 10 5 AMX Bits and Address Multiplex Output Row Address Column Address AMX1 AMX0 Shift Amount Output Pins Output Address Output Address Output Pins 0 0 9 bit A21 A15 A21 A15 A21 A0 A21 A0 A14 A0 A23 A9 0 1 10 bit A21 A14 A21 A14 A21 A0 A21 A0 A13 A0 A23 A10 1 0 11 bit A21 A13 A21 A13 A21 A0 A21 A0 A12 A0 A23 A11 1 1...

Page 228: ...h transfer of these actual byte locations CASHH bits 31 24 CASHL bits 23 16 CASH bits 15 8 and CASL bits 7 0 However the signals for ordinary space WRx and RD are also output during the DMAC single transfer column address cycle period Tp is the precharge cycle Tr is the RAS assert cycle Tc is the CAS assert cycle and Tc2 is the read data fetch cycle Tp Tr Tc1 Tc2 CK Write Read Address Data RAS CAS...

Page 229: ... waits inserted is shown in figures 10 8 through 10 11 External waits can be inserted at the time of software waits 2 3 The sampling location is the same as that of ordinary space at one cycle before the Tc2 cycle clock rise Wait cycles are extended by external waits Tp Tr Tc1 Tcw1 Tc2 CK Write Read Address Data RAS CASx RDWR Data RDWR CASx RAS Row Column Figure 10 8 DRAM Bus Cycle Normal Mode TPC...

Page 230: ...192 Tp Tr Trw Tc1 Tcw1 Tcw2 Tcw2 Tpw CK Write Read Address Data RAS CASx RDWR Data RDWR CASx RAS Row Column Figure 10 9 DRAM Bus Cycle Normal Mode TPC 1 RCD 1 Two Waits ...

Page 231: ...193 Tp Tc1 Tcw1 Tcw2 Tcw3 Tc2 Tr CK Write Read Address Data RAS CASx RDWR Data RDWR CASx RAS Row Column Figure 10 10 DRAM Bus Cycle Normal Mode TPC 0 RCD 0 Three Waits ...

Page 232: ...194 Tp Tc1 Tcw1 Tcw2 Tcw0 Tc2 Tr CK Write Read Address Data RAS CASx RDWR Data RDWR CASx RAS Row Column WAIT Figure 10 11 DRAM Bus Cycle Normal Mode TPC 0 RCD 0 Two Waits Wait Due to WAIT Signal ...

Page 233: ...ycle High Speed Page Mode RAS Down Mode There are some instances where even if burst operation is selected continuous accesses to DRAM will not occur but another space will be accessed instead part way through the access In such cases if the RAS signal is maintained at low level during the time the other space is accessed it is possible to continue burst operation at the time the next DRAM same ro...

Page 234: ...ta CS space Tp Tr Tc1 Tc2 T1 T2 Tp Tr Tc1 Tc2 Column Column Row Row Figure 10 13 DRAM Access Normal Operation RAS Up Mode CK RAS CASx DRAM access DRAM access CS space access Address Data Row Column CS space Tp Tr Tc1 Tc2 T1 T2 Tc1 Tc2 Column Figure 10 14 RAS Down Mode ...

Page 235: ...rval prescribed for the DRAM being used When a clock is selected with the CKS2 CKS0 bits of the RSTCR RTCNT starts counting up from the value at that time The RTCNT value is constantly compared to the RTCOR value and a CBR refresh is performed when the two match RTCNT is cleared at that time and the count starts again Figure 10 15 shows the timing for the CBR refresh operation The number of RAS as...

Page 236: ...sh then access only after doing individual refreshes for all row addresses within the time prescribed for the particular DRAM For external bus right requests during self refreshes to preserve DRAM data at the time of releasing the bus rights only CASx RAS and RDWR are output and the bus rights are released to the external device with the self refresh maintained Consequently do not perform DRAM acc...

Page 237: ... space is accessed addresses and data are multiplexed When the A14 address bit is 0 the bus size becomes 8 bit and addresses and data are input and output through the D7 D0 pins When the A14 address bit is 1 the bus size becomes 16 bit and address output and data I O occur through the D15 D0 pins Access for the address data multiplex I O space is controlled by the AH RD and WRx signals Address dat...

Page 238: ...e same as during ordinary space accesses The timing for one software wait one external wait inserted is shown in figure 10 18 CK CS3 AH RD Data WRx Data WAIT Address Ta1 Ta2 Ta3 Ta4 T1 TW TWo T2 Read Write Address output Address output Data output Data input Figure 10 18 Address Data Multiplex I O Space Access Wait State Timing One Software Wait One External Wait ...

Page 239: ...om a slow device is completed data buffers may not go off in time to prevent data conflicts with the next access If there is a data conflict during memory access the problem can be solved by inserting a wait in the access cycle To enable detection of bus cycle starts waits can be inserted between access cycles during continuous accesses of the same CS space by negating the CSn signal once 10 6 1 P...

Page 240: ...dle cycle WRx Address T1 T2 T1 T2 Tidle Figure 10 20 Idle Cycle Insertion Example IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces or for this LSI to do write accesses In the same manner IW21 and IW20 specify the number of idle cycles after a CS2 space read IW11 and IW10 the number after a CS1 space read and IW01 and IW00 the numb...

Page 241: ... T2 Tidle Figure 10 21 Same Space Consecutive Access Idle Cycle Insertion Example 10 7 Bus Arbitration The SH7040 series has a bus arbitration function that when a bus release request is received from an external device releases the bus to that device It also has two internal bus masters the CPU and the DMAC DTC The priority ranking for determining bus right transfer between these bus masters is B...

Page 242: ... this LSI will not be able to perform the refresh operation and the DRAM contents cannot be guaranteed Figure 10 22 shows the bus right release procedure BREQ Low SH704X BREQ accepted Strobe pin high level output Address data strobe pin high impedance Bus right release response Bus right release status External device Bus right request BACK confirmation Bus right acquisition BACK Low Figure 10 22 ...

Page 243: ...nput ports in power on reset they should be handled e g pulled down as necessary SH704x 32k 8 bits CE OE CSn RD A0 A14 D0 D7 A0 A14 I O0 I O7 ROM Figure 10 23 8 Bit Data Bus Width ROM Connection SH704x 256k 16 bits ROM CE OE CSn RD A0 A1 A18 D0 D15 A0 A17 I O0 I O15 Figure 10 24 16 Bit Data Bus Width ROM Connection ...

Page 244: ...9 D16 D31 D0 D15 A0 A17 A0 A17 I O0 I O15 I O0 I O15 256k 16 bits ROM Figure 10 25 32 Bit Data Bus Width ROM Connection SH704x CSn RD WRL WE CS OE A0 A16 A0 A16 D0 D7 I O0 I O7 123k 8 bits SRAM Figure 10 26 8 Bit Data Bus Width SRAM Connection ...

Page 245: ...207 SH704x 128k 8 bits SRAM CSn RD CS OE A0 A1 A17 A0 A16 WRH WE D8 D15 I O0 I O7 WRL D0 D7 CS OE A0 A16 WE I O0 I O7 Figure 10 27 16 Bit Data Bus Width SRAM Connection ...

Page 246: ...A0 A1 A2 A18 A0 A16 WRHH WE D24 D31 I O0 I O7 WRHL D16 D23 D0 D7 WRL WRH D8 D15 CS OE A0 A16 WE I O0 I O7 CS OE A0 A16 WE I O0 I O7 I O0 I O7 CS OE A0 A16 WE 128k 8 bits SRAM Figure 10 28 32 Bit Data Bus Width SRAM Connection ...

Page 247: ... WE A0 A9 CAS I O0 I O7 OE 512k 8 bits DRAM Figure 10 29 8 Bit Data Bus Width DRAM Connection RAS RAS RDWR WE A0 OE A1 A9 CASH UCAS CASL LCAS AD0 AD15 I O0 I O15 SH704x 256k 16 bits DRAM A0 A8 Figure 10 30 16 Bit Data Bus Width DRAM Connection ...

Page 248: ... Access On chip peripheral I O registers are accessed from the bus state controller as shown in table 10 6 Table 10 6 On Chip Peripheral I O Register Access On chip Peripheral Module SCI MTU POE INTC PFC PORT CMT A D UBC WDT DMAC DTC CACHE Connected bus width 8bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit Access cycle 2cyc 2cyc 2cyc 2cyc 2cyc 2cyc 3cyc 3cyc 3cyc 3cyc 3cyc Note A ...

Page 249: ...Bus is not Released Figure 10 32 One Bus Cycle 10 10 CPU Operation when Program is in External Memory In the SH7040 Series two words equivalent to two instructions are normally fetched in a single instruction fetch This is also true when the program is located in external memory irrespective of whether the external memory bus width is 8 or 16 bits If the program counter value immediately after the...

Page 250: ...212 ...

Page 251: ...e other is accessed by address One transfer unit of data is transferred in each bus cycle Dual address mode Both the transfer source and transfer destination are accessed by address Dual address mode can be direct or indirect address transfer Direct access Values set in a DMAC internal register indicate the accessed address for both the transfer source and transfer destination Two bus cycles are r...

Page 252: ...ed either by falling edge or by low level External requests can only be received on channels 0 or 1 Requests from on chip peripheral modules Transfer requests from on chip modules such as SCI or A D These can be received by all channels Auto request The transfer request is generated automatically within the DMAC Selectable bus modes Cycle steal mode or burst mode Two types of DMAC channel priority...

Page 253: ...troller On chip peripheral module DARn DMATCRn CHCRn DMAOR MTU SCI0 SCI1 A D converter DEIn External ROM External RAM External I O memory mapped External I O with acknowledge DACK0 DACK1 DRAK0 DRAK1 SARn DARn DMATCRn CHCRn DMAOR n DMAC source address register DMAC destination address register DMAC transfer count register DMAC channel control register DMAC operation register 0 1 2 3 Note A D1 for A...

Page 254: ...tput from channel 0 to external device DREQ0 acceptance confirmation DRAK0 O Sampling receive acknowledge output for DMA transfer request input from external source 1 DMA transfer request DREQ1 I DMA transfer request input from external device to channel 1 DMA transfer request acknowledge DACK1 O DMA transfer strobe output from channel 1 to external device DREQ1 acceptance confirmation DRAK1 O Sam...

Page 255: ...C4 32 bit 16 32 2 DMA transfer count register 0 DMATCR0 R W Undefined H FFFF86C8 32 bit 16 32 3 DMA channel control register 0 CHCR0 R W 1 H 00000000 H FFFF86CC 32 bit 16 32 2 1 DMA source address register 1 SAR1 R W Undefined H FFFF86D0 32 bit 16 32 2 DMA destination address register 1 DAR1 R W Undefined H FFFF86D4 32 bit 16 32 2 DMA transfer count register 1 DMATCR1 R W Undefined H FFFF86D8 32 b...

Page 256: ... in bits 1 and 2 of the DMAOR to clear flags No other writes are allowed 2 For 16 bit access of SAR0 SAR3 DAR0 DAR3 and CHCR0 CHCR3 the 16 bit value on the side not accessed is held 3 DMATCR has a 24 bit configuration bits 0 23 Writing to the upper 8 bits bits 24 31 is invalid and these bits always read 0 4 Do not make 32 bit access for DMAOR 11 2 Register Descriptions 11 2 1 DMA Source Address Re...

Page 257: ...DMA transfer they indicate the next destination address In single address mode DAR values are ignored when a device with DACK has been specified as the transfer destination Specify a 16 bit or 32 bit boundary address when doing 16 bit or 32 bit data transfers Operation cannot be guaranteed on any other address The initial value after power on resets or in software standby mode is undefined These r...

Page 258: ...s The data for the upper 8 bits of a DMATCR is 0 when read Always write 0 The initial value after power on resets or in software standby mode is undefined These registers are not initialized with manual reset Always write 0 to the upper 8 bits of a DMATCR Bit 31 30 29 28 27 26 25 24 Initial value R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 Initial value R W R W R W R W R W R W R W R W R W Bit ...

Page 259: ...RS1 RS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 DS 2 TM TS1 TS0 IE TE DE Initial value 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W 1 R W Notes 1 TE bit Allows only 0 write after reading 1 2 The DI RO RL AM AL or DS bit may be absent depending on the channel Bits 31 21 Reserved bits Data are 0 when read The write value always be 0 Bit 20 Direct Indirect...

Page 260: ...tput DRAK with active high initial value 1 Output DRAK with active low Bit 17 Acknowledge Mode AM In dual address mode selects whether to output DACK in the data write cycle or data read cycle In single address mode DACK is always output irrespective of the setting of this bit This bit is valid only for CHCR0 and CHCR1 It always reads as 0 for CHCR2 and CHCR3 and cannot be modified Bit 17 AM Descr...

Page 261: ...the DMA transfer source address These bit specifications are ignored when transferring data from an external device to address space in single address mode Bit 13 SM1 Bit 12 SM0 Description 0 0 Source address fixed initial value 0 1 Source address incremented 1 during 8 bit transfer 2 during 16 bit transfer 4 during 32 bit transfer 1 0 Source address decremented 1 during 8 bit transfer 2 during 16...

Page 262: ...CI1 RXI1 Notes External request designations are valid only for channels 0 and 1 No transfer request sources can be set for channels 2 or 3 ADI1 for A mask Bit 7 Reserved bits Data is 0 when read The write value always be 0 Bit 6 DREQ Select DS Sets the sampling method for the DREQ pin in external request mode to either low level detection or falling edge detection This bit is valid only with CHCR...

Page 263: ...t not generated after DMATCR specified transfer count initial value 1 Interrupt request enabled on completion of DMATCR specified number of transfers Bit 1 Transfer End Flag TE This bit is set to 1 after the number of data transfers specified by the DMATCR At this time if the IE bit is set to 1 an interrupt request is generated If data transfer ends before TE is set to 1 for example due to an NMI ...

Page 264: ...pended If the DE bit has been set but TE 1 then if the DME bit of the DMAOR is 0 and the NMI or AE bit of the DMAOR is 1 transfer enable mode is not entered 11 2 5 DMAC Operation Register DMAOR The DMAOR is a 16 bit read write register that specifies the transfer mode of the DMAC Register values are initialized to 0 during power on reset or in software standby mode Manual reset does not initialize...

Page 265: ...e a 1 to the AE bit Clearing is effected by 0 write after 1 read Bit 2 AE Description 0 No address error DMA transfer enabled initial value Clearing condition Write AE 0 after reading AE 1 1 Address error DMA transfer disabled Setting condition Address error due to DMAC Bit 1 NMI Flag NMIF Indicates input of an NMI This bit is set irrespective of whether the DMAC is operating or suspended If this ...

Page 266: ...fer mode The bus mode can be either burst or cycle steal 11 3 1 DMA Transfer Flow After the DMA source address registers SAR DMA destination address registers DAR DMA transfer count register DMATCR DMA channel control registers CHCR and DMA operation register DMAOR are set to the desired transfer conditions the DMAC transfers data according to the following procedure 1 The DMAC checks to see if tr...

Page 267: ... IE 1 No Yes No Yes No Yes Yes No Yes No 3 2 Start Transfer aborted Notes 1 2 3 In auto request mode transfer begins when NMIF AE and TE are all 0 and the DE and DME bits are set to 1 DREQ level detection in burst mode external request or cycle steal mode DREQ edge detection in burst mode external request or auto request mode in burst mode DMATCR 0 Transfer request occurs 1 DE DME 1 and NMIF AE TE...

Page 268: ...nsfer is enabled DE 1 DME 1 TE 0 NMIF 0 AE 0 a transfer is performed upon a request at the DREQ input Choose to detect DREQ by either the falling edge or low level of the signal input with the DS bit of CHCR0 CHCR3 DS 0 is level detection DS 1 is edge detection The source of the transfer request does not have to be the data transfer source or destination Table 11 3 Selecting External Request Modes...

Page 269: ... 0 1 MTU 2 TGI3A Any 1 Any 1 Burst cycle steal 1 0 1 0 MTU 2 TGI4A Any 1 Any 1 Burst cycle steal 1 0 1 1 A D ADI 5 ADDR 4 Any 1 Burst cycle steal 1 1 0 0 SCI0 3 transmit block TxI0 Any 1 TDR0 Burst cycle steal 1 1 0 1 SCI0 3 transmit block RxI0 RDR0 Any 1 Burst cycle steal 1 1 1 0 SCI1 3 transmit block TxI1 Any 1 TDR1 Burst cycle steal 1 1 1 1 SCI1 3 transmit block RxI1 RDR1 Any 1 Burst cycle stea...

Page 270: ... modes the priority levels among the channels remain fixed The following priority orders are available for fixed mode CH0 CH1 CH2 CH3 CH0 CH2 CH3 CH1 CH2 CH0 CH1 CH3 These are selected by settings of the PR1 and PR0 bits of the DMA operation register DMAOR Round Robin Mode In round robin mode each time the transfer of one transfer unit byte word or long word ends on a given channel that channel re...

Page 271: ...ously Immedi ately thereafter if there is a transfer request for channel 1 only channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down When channel 1 is given the lowest priority the priority of channel 0 which was above channel 1 is also shifted simultaneously Channel 0 is given the lowest priority Priority after transfer Priority after trans...

Page 272: ...hifts to the lowest priority level 5 At this point channel 1 has a higher priority level than channel 3 so the channel 1 transfer comes first channel 3 is on transfer standby 6 When the channel 1 transfer ends channel 1 shifts to the lowest priority level 7 Channel 3 transfer begins 8 When the channel 3 transfer ends channel 3 and channel 2 priority levels are lowered giving channel 3 the lowest p...

Page 273: ...heral Module External device with DACK Not available Single Single Not available Not available External memory Single Dual Dual Dual Dual Memory mapped external device Single Dual Dual Dual Dual On chip memory Not available Dual Dual Dual Dual On chip peripheral module Not available Dual Dual Dual Dual Notes 1 Single Single address mode 2 Dual Dual address mode includes both direct address mode an...

Page 274: ...e Two types of transfers are possible in the single address mode a transfers between external devices with DACK and memory mapped external devices and b transfers between external devices with DACK and external memory The only transfer requests for either of these is the external request DREQ Figure 11 6 shows the DMA transfer timing for the single address mode ...

Page 275: ...ss Mode Dual address mode is used for access of both the transfer source and destination by address Transfer source and destination can be accessed either internally or externally Dual address mode is subdivided into two other modes direct address transfer mode and indirect address transfer mode Direct Address Transfer Mode Data is read from the transfer source during the data read cycle and writt...

Page 276: ...SAR DAR Data buffer SAR DAR The SAR value is taken as the address and data is read from the transfer source module and stored temporarily in the DMAC 1st bus cycle 2nd bus cycle The DAR value is taken as the address and data stored in the DMAC s data buffer is written to the transfer destination module DMAC DMAC Figure 11 7 Direct Address Operation during Dual Address Mode ...

Page 277: ...tination address Transfer source address CK 1st cycle 2nd cycle A21 A0 CSn D15 D0 RD WRH WRL DACK Note Transfer between external memories with DACK are output during read cycle Figure 11 8 Example of Direct Address Transfer Timing in Dual Address Mode ...

Page 278: ... to the address specified by the transfer destination address register ending one cycle of DMA transfer In indirect address mode figure 11 9 transfer destination transfer source and indirect address storage destination are all 16 bit external memory locations and transfer in this example is conducted in 16 bit or 8 bit units Timing for this transfer example is shown in figure 11 10 In indirect add...

Page 279: ...ule Temporary buffer The value in the temporary buffer is taken as the address and data is read from the transfer source module to the data buffer SAR3 DAR3 Data buffer Address bus Data bus Memory Transfer source module Transfer destination module Temporary buffer The DAR3 value is taken as the address and the value in the data buffer is written to the transfer destination module Note Memory trans...

Page 280: ...ad cycle 1st 2nd 3rd NOP cycle Data read cycle 4th Data write cycle CK A21 A0 CSn D15 D0 Internal address bus Internal data bus DMAC indirect address buffer DMAC data buffer RD WRH WRL Notes 1 2 The internal address bus is controlled by the port and does not change DMAC does not fetch value until 32 bit data is read from the internal data bus External memory space has 16 bit width Figure 11 10 Dua...

Page 281: ...nation is 2 cycle access space so two data write cycles are required One NOP cycle is required until the data read as the indirect address is output to the address bus Internal address bus Internal data bus DMAC indirect address buffer DMAC data buffer CK Transfer source address NOP NOP Indirect address Transfer destination address Indirect address Indirect address Transfer data Transfer data Tran...

Page 282: ...in the cycle steal mode Transfer conditions are dual address mode and DREQ level detection CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU DREQ Bus cycle Bus control returned to CPU Read Write Write Read Figure 11 12 DMA Transfer Example in the Cycle Steal Mode Burst Mode Once the bus right is obtained the transfer is performed continuously until the transfer end condition is satisfied In the external...

Page 283: ...mapped external device and on chip peripheral module Any 2 B C 3 8 16 32 4 0 3 5 On chip memory and on chip memory Any 1 B C 8 16 32 0 3 5 On chip memory and on chip peripheral module Any 2 B C 3 8 16 32 4 0 3 5 On chip peripheral module and on chip peripheral module Any 2 B C 3 8 16 32 4 0 3 5 Notes 1 External request auto request or on chip peripheral module request enabled However in the case o...

Page 284: ...CPU CPU Priority Round robin mode ch0 Cycle steal mode ch1 Burst mode DMAC ch1 burst mode Figure 11 14 Bus Handling when Multiple Channels Are Operating 11 3 10 Number of Bus Cycle States and DREQ Pin Sample Timing Number of States in Bus Cycle The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller BSC just as it is when the CPU is the bus m...

Page 285: ...her edge or low level DREQ detection is used For example DMAC transfer begins figure 11 15 at the earliest three cycles from the first sampling timing The second sampling begins at the start of the transfer one bus cycle prior to the start of the DMAC transfer initiated by the first sampling i e from the start of the CPU 3 transfer At this point if DREQ detection has not occurred sampling is execu...

Page 286: ...8 CK DREQ DRAK Bus cycle DACK CPU 3 CPU 4 CPU 5 CPU 2 CPU 1 1st sampling 2nd sampling DMAC R DMAC R DMAC W DMAC W DMAC W DMAC R Figure 11 15 Cycle Steal Dual Address and Level Detection Fastest Operation ...

Page 287: ...PU DMAC R DMAC R DMAC W 1st sampling 2nd sampling Note With cycle steal and dual address operation sampling timing is the same whether DREQ detection is by level or by edge Figure 11 16 Cycle Steal Dual Address and Level Detection Normal Operation ...

Page 288: ... this case transfer begins at earliest three cycles after the first DREQ sampling The second sampling begins from the start of the transfer one bus cycle before the start of the first DMAC transfer In single address mode the DACK signal is output during the DMAC transfer period ...

Page 289: ...251 CK DREQ DRAK Bus cycle DACK CPU CPU CPU CPU CPU DMAC DMAC DMAC Figure 11 17 Cycle Steal Single Address and Level Detection Fastest Operation ...

Page 290: ...252 CK DREQ DRAK Bus cycle DACK CPU CPU DMAC CPU DMAC CPU CPU Figure 11 18 Cycle Steal Single Address and Level Detection Normal Operation ...

Page 291: ...ming of the first sampling The second sampling also begins from the start of the transfer one bus cycle before the start of the first DMAC transfer In burst mode as long as transfer requests are issued DMAC transfer continues Therefore the transfer one bus cycle before the start of the DMAC transfer may be a DMAC transfer In burst mode the DACK output period is the same as that of cycle steal mode...

Page 292: ...254 CK DREQ DRAK Bus cycle DACK CPU CPU CPU CPU DMAC R DMAC W DMAC R DMAC R DMAC W DMAC R DMAC W Figure 11 19 Burst Mode Dual Address and Level Detection Fastest Operation ...

Page 293: ...255 CK DREQ DRAK Bus cycle DACK CPU CPU DMAC R DMAC R DMAC R CPU DMAC W DMAC W Figure 11 20 Burst Mode Dual Address and Level Detection Normal Operation ...

Page 294: ...counted either at the start of the second sampling transfer one bus cycle before the start of the first DMAC transfer Therefore the second sampling is not conducted from the bus cycle starting the dummy cycle but from the start of the CPU 3 bus cycle Thereafter as long the DREQ is continuously sampled no dummy cycle is inserted DREQ sampling timing during this period begins from the start of the t...

Page 295: ...K DREQ DRAK Bus cycle DACK CPU 4 CPU 1 CPU 2 CPU 3 Dummy DMAC Dummy 2nd sampling 1st sampling 3rd sampling 4th sampling DMAC DMAC Figure 11 21 Burst Mode Single Address and Level Detection Fastest Operation ...

Page 296: ...258 CK DREQ DRAK Bus cycle DACK CPU CPU Dummy DMAC CPU DMAC DMAC Figure 11 22 Burst Mode Single Address and Level Detection Normal Operation ...

Page 297: ...st sampling Thereafter DMAC transfer continues until the end of the data transfer count set in the TCR DREQ sampling is not conducted during this period Therefore DRAK is output on the first cycle only When DMAC transfer is resumed after being halted by a NMI or address error be sure to reinput an edge request The remaining transfer restarts after the first DRAK output The DACK output period in bu...

Page 298: ...260 CK DREQ DRAK Bus cycle DACK CPU CPU CPU DMAC R DMAC R DMAC R DMAC R DMAC W DMAC W DMAC W DMAC W Figure 11 23 Burst Mode Dual Address and Edge Detection ...

Page 299: ...ot output Nor is the number of DMAC transfers counted Thereafter DMAC transfer continues until the data transfer count set in the DMATCR has ended DREQ sampling is not conducted during this period Therefore DRAK is output on the first cycle only When DMAC transfer is resumed after being halted by a NMI or address error be sure to reinput an edge request DRAK is output once and the remaining transf...

Page 300: ...262 CK DREQ DRAK Bus cycle DACK CPU DMAC DMAC DMAC DMAC CPU CPU Dummy Figure 11 24 Burst Mode Single Address and Edge Detection ...

Page 301: ...ntrol 4th count CHCR2 DMATCR2 SAR2 RO bit 1 Count signal Reload signal Reload signal Address bus Figure 11 25 Source Address Reload Function CK Internal address bus Internal data bus SAR2 DAR2 DAR2 DAR2 DAR2 SAR2 2 SAR2 4 SAR2 6 SAR2 DAR2 SAR2 data SAR2 2 data SAR2 4 data SAR2 6 data SAR2 data 1st channel 2 transfer 2nd channel 2 transfer 3rd channel 2 transfer 4th channel 2 transfer 5th channel 2...

Page 302: ... Conditions There are two ending conditions A transfer ends when the value of the channel s DMA transfer count register DMATCR is 0 or when the DE bit of the channel s CHCR is cleared to 0 When DMATCR is 0 When the DMATCR value becomes 0 and the corresponding channel s DMA transfer ends the transfer end flag bit TE is set in the CHCR If the IE interrupt enable bit has been set a DMAC interrupt DEI...

Page 303: ...cess is automatically divided into two word accesses requiring two bus cycles six basic clock cycles These two bus cycles are executed consecutively a different bus cycle is never inserted between the two word accesses This applies to both write accesses and read accesses 11 4 Examples of Use 11 4 1 Example of DMA Transfer between On Chip SCI and External Memory In this example on chip serial comm...

Page 304: ...H 00400000 Transfer destination external device with DACK DAR1 access by DACK Transfer count 32 times DMATCR1 H 00000020 Transfer source address decremented CHCR1 H 00002269 Transfer destination address setting ineffective Transfer request source external pin DREQ1 edge detection Bus mode burst Transfer unit word No interrupt request generation at end of transfer Channel priority ranking 2 0 1 3 D...

Page 305: ...ta is written to the on chip memory address H FFFFF001 Because a byte size transfer was performed the SAR and DAR values at this point are H FFFF83F1 and H FFFFF001 respectively Also because this is a burst transfer the bus rights remain secured so continuous data transfer is possible When four transfers are completed if the address reload is off execution continues with the fifth and sixth transf...

Page 306: ...ress reload is on or off 3 Designate burst mode when using the address reload function There are cases where abnormal operation will result if it is executed in cycle steal mode 4 Designate a multiple of four for the TCR value when using the address reload function There are cases where abnormal operation will result if anything else is designated To execute transfers after the fifth one when the ...

Page 307: ...ta is written to the on chip memory address H FFFFF001 Because a byte size transfer was performed the SAR and DAR values at this point are H FFFF8409 and H FFFFF001 respectively Also because this is a burst transfer the bus rights remain secured so continuous data transfer is possible When four transfers are completed if the address reload is off execution continues with the fifth and sixth transf...

Page 308: ...ess reload is on or off 3 Designate burst mode when using the address reload function There are cases where abnormal operation will result if it is executed in cycle steal mode 4 Designate a multiple of four for the TCR value when using the address reload function There are cases where abnormal operation will result if anything else is designated To execute more than four transfers with the addres...

Page 309: ...ata then that data is stored in the address designated by the DAR In the table 11 13 example when a transfer request from the TDR1 of SCI1 is generated a read of the address located at H 00400000 which is the value set in SAR3 is performed first The data H 00450000 is stored at this H 00400000 address and the DMAC first reads this H 00450000 value It then uses this read value of H 00450000 as an a...

Page 310: ...DMATCR count becomes 0 and the DMA transfer ends normally always write a 0 to the DMATCR even when executing the maximum number of transfers on the same channel There are instances where abnormal operation will result if this is not done 8 Designate burst mode as the transfer mode when using the address reload function There are instances where abnormal operation will result in cycle steal mode 9 ...

Page 311: ...wo or more timer counters TCNT can be written to simultaneously Two or more timer counters can be simultaneously cleared by a compare match or input capture Counter synchronization functions enable synchronized register input output PWM mode PWM output can be provided with any duty cycle When combined with the counter synchronizing function enables up to twelve phase PWM output With channels 0 2 s...

Page 312: ...ow interrupt which can be requested independently Channels 1 and 2 have two compare match input capture interrupts one overflow interrupt and one underflow interrupt which can be requested independently Automatic transfer of register data Block transfer 1 word data transfers and 1 byte data transfers are possible through DTC or DMAC activation A D converter conversion start trigger can be generate...

Page 313: ...pare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 Yes Yes Yes Yes Yes match output 1 Yes Yes Yes Yes Yes Toggle Yes Yes Yes Yes Yes Input capture function Yes Yes Yes Yes Yes Synchronization Yes Yes Yes Yes Yes Buffer operation Yes No No Yes No PWM mode 1 Yes Yes Yes Yes ...

Page 314: ...e TGR4A com pare match or input capture Interrupt sources Compare match input capture 0A Compare match input capture 1A Compare match input capture 2A Compare match input capture 3A Compare match input capture 4A Compare match input capture 0B Compare match input capture 1B Compare match input capture 2B Compare match input capture 3B Compare match input capture 4B Compare match input capture 0C O...

Page 315: ...TGRC I O pins Channel 3 TIOC3A TIOC3B TIOC3C TIOC3D Channel 4 TIOC4A TIOC4B TIOC4C TIOC4D Clock input Internal clock φ 1 φ 4 φ 16 φ 64 φ 256 φ 1024 I O pins Channel 0 TIOC0A TIOC0B TIOC0C TIOC0D External clock TCLKA TCLKB TCLKC TCLKD Channel 1 TIOC1A TIOC1B Channel 2 TIOC2A TIOC2B Internal data bus A D conversion start request signal Interrupt request signals Channel 3 TGI3A TGI3B TGI3C TGI3D TGI3...

Page 316: ...WM output pin Input capture output compare match 0B TIOC0B I O TGR0B input capture input output compare output PWM output pin Input capture output compare match 0C TIOC0C I O TGR0C input capture input output compare output PWM output pin Input capture output compare match 0D TIOC0D I O TGR0D input capture input output compare output PWM output pin 1 Input capture output compare match 1A TIOC1A I O...

Page 317: ...M reset synchronous PWM mode PWM output U phase output pin 4 Input capture output compare match 4A TIOC4A I O TGR4A input capture input output compare output PWM output pin In complementary PWM reset synchronous PWM mode PWM output V phase output pin Input capture output compare match 4B TIOC4B I O TGR4B input capture input output compare output pin In complementary PWM reset synchronous PWM mode ...

Page 318: ...ster 0 TIER0 R W H 40 H FFFF8264 Timer status register 0 TSR0 R W 2 H C0 H FFFF8265 Timer counter 0 TCNT0 R W H 0000 H FFFF8266 16 32 General register 0A TGR0A R W H FFFF H FFFF8268 General register 0B TGR0B R W H FFFF H FFFF826A General register 0C TGR0C R W H FFFF H FFFF826C General register 0D TGR0D R W H FFFF H FFFF826E 1 Timer control register 1 TCR1 R W H 00 H FFFF8280 8 16 32 Timer mode reg...

Page 319: ...02 Timer I O control register 3H TIOR3H R W 3 H 00 H FFFF8204 Timer I O control register 3L TIOR3L R W 3 H 00 H FFFF8205 Timer interrupt enable register 3 TIER3 R W 3 H 40 H FFFF8208 Timer status register 3 TSR3 R W 2 H C0 H FFFF822C 8 16 32 Timer counter 3 TCNT3 R W 3 H 0000 H FFFF8210 16 32 General register 3A TGR3A R W 3 H FFFF H FFFF8218 General register 3B TGR3B R W 3 H FFFF H FFFF821A Genera...

Page 320: ... TOER R W 3 H C0 H FFFF820A 8 16 32 Timer output control register TOCR R W 3 H 00 H FFFF820B Timer gate control register TGCR R W 3 H 80 H FFFF820D Timer cycle data register TCDR R W 3 H FFFF H FFFF8214 16 32 Timer dead time data register TDDR R W 3 H FFFF H FFFF8216 Timer subcounter TCNTS R H 0000 H FFFF8220 16 32 Timer cycle buffer register TCBR R W H FFFF H FFFF8222 Notes 1 16 bit registers TCN...

Page 321: ...et or the standby mode Manual reset does not initialize TCR Channels 0 3 4 TCR0 TCR3 TCR4 Bit 7 6 5 4 3 2 1 0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Channels 1 2 TCR1 TCR2 Bit 7 6 5 4 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 7 5 Counter Clear 2 1 ...

Page 322: ... cleared because the buffer registers have priority and compare match input captures do not occur Channels 1 2 Bit 7 Reserved 1 Bit 6 CCLR1 Bit 5 CCLR0 Description 0 0 0 TCNT clear disabled initial value 1 TCNT is cleared by TGRA compare match or input capture 1 0 TCNT is cleared by TGRB compare match or input capture 1 Synchronizing clear TCNT is cleared in synchronization with clear of other cha...

Page 323: ...annel Table 12 4 shows the possible settings for each channel Table 12 4 MTU Clock Sources Internal Clock Other Channel External Clock Chan nel φ 1 φ 4 φ 16 φ 64 φ 256 φ 1024 Overflow Underflow TCL KA TCL KB TCL KC TCL KD 0 O O O O X X X O O O O 1 O O O O O X O O O X X 2 O O O O X O X O O O X 3 O O O O O O X O O X X 4 O O O O O O X O O X X Note Symbols O Setting possible X Setting not possible Cha...

Page 324: ...NT2 overflow underflow Note These settings are ineffective when channel 1 is in phase counting mode Channel 2 Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock count with φ 1 initial value 1 Internal clock count with φ 4 1 0 Internal clock count with φ 16 1 Internal clock count with φ 64 1 0 0 External clock count with the TCLKA pin input 1 External clock count with the TCLKB pi...

Page 325: ...1024 1 0 External clock count with the TCLKA pin input 1 External clock count with the TCLKB pin input Channel 4 Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock count with φ 1 initial value 1 Internal clock count with φ 4 1 0 Internal clock count with φ 16 1 Internal clock count with φ 64 1 0 0 Internal clock count with φ 256 1 Internal clock count with φ 1024 1 0 External clo...

Page 326: ...DR2 Bit 7 6 5 4 3 2 1 0 MD3 MD2 MD1 MD0 Initial value 1 1 0 0 0 0 0 0 R W R R R R R W R W R W R W Bits 7 6 Reserved These bits are reserved They always read as 1 and cannot be modified Bit 5 Buffer Operation B BFB Designates whether to use the TGRB register for normal operation or buffer operation in combination with the TGRD register When using TGRD as a buffer register no TGRD register input cap...

Page 327: ... 2 1 Phase counting mode 2 2 1 0 Phase counting mode 3 2 1 Phase counting mode 4 2 1 0 0 0 Reset synchronous PWM mode 3 1 Reserved do not set 1 0 Reserved do not set 1 Reserved do not set 1 0 0 Reserved do not set 1 Complementary PWM mode 1 transmit at peak 3 1 0 Complementary PWM mode 2 transmit at valley 3 1 Complementary PWM mode 3 transmit at peak and valley 3 Notes 1 PWM mode 2 can not be set...

Page 328: ... W R W R W R W R W R W R W R W Bits 7 4 I O Control B3 B0 IOB3 IOB0 These bits set the TGRB register function Bits 3 0 I O Control A3 B0 IOA3 IOA0 These bits set the TGRA register function Channels 0 3 4 TIOR0L TIOR3L TIOR4L Bit 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note When the TGRC or TGRD registers are set for ...

Page 329: ... compare match 1 compare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR0B Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC0B pin 1 0 0 register Capture Input ...

Page 330: ...h 1 compare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR0A Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC0A pin 1 0 0 register Capture Input capture 1 inp...

Page 331: ...isabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR0D Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC0D pin 1 0 0 register Capture Input capture 1 input source on TCNT1 1 0 is channel 1 count up count down 1 count clock N...

Page 332: ...tial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR0C Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC0C pin 1 0 0 register Capture Input capture 1 input source on TCNT1 1 0 is channel 1 count up count down 1 count clock Note When the ...

Page 333: ...ompare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR1B Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC1B pin 1 0 0 register Capture input Input capture 1 so...

Page 334: ...gle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR1A Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC1A pin 1 0 0 register Capture input Input capture 1 source is TGR0A o...

Page 335: ...n compare match 1 compare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR2B Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC2B pin 1 0 0 register Input capture...

Page 336: ...ch 1 compare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR2A Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC2A pin 1 0 0 register Input capture on rising ed...

Page 337: ...n compare match 1 compare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR3B Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC3B pin 1 0 0 register Input capture...

Page 338: ...ch 1 compare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR3A Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC3A pin 1 0 0 register Input capture on rising ed...

Page 339: ...disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR3D Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC3D pin 1 0 0 register Input capture on rising edge 1 Input capture on falling edge 1 0 Input capture on both edges 1 No...

Page 340: ...itial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR3C Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC3C pin 1 0 0 register Input capture on rising edge 1 Input capture on falling edge 1 0 Input capture on both edges 1 Note When the B...

Page 341: ...n compare match 1 compare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR4B Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC4B pin 1 0 0 register Input capture...

Page 342: ...ch 1 compare is 0 Toggle output on compare match 1 0 0 register Output disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR4A Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC4A pin 1 0 0 register Input capture on rising ed...

Page 343: ...disabled 1 Initial Output 0 on compare match 1 0 output Output 1 on compare match 1 is 1 Toggle output on compare match 1 0 0 0 TGR4D Capture Input capture on rising edge 1 is an input source Input capture on falling edge 1 0 input is the Input capture on both edges 1 capture TIOC4D pin 1 0 0 register Input capture on rising edge 1 Input capture on falling edge 1 0 Input capture on both edges 1 No...

Page 344: ... falling edge 1 0 input is the Input capture on both edges 1 capture TIOC4C pin 1 0 0 register Input capture on rising edge 1 Input capture on falling edge 1 0 Input capture on both edges 1 Note When the BFA bit of TMDR4 is set to 1 and TGR4C is being used as a buffer register these settings become ineffective and input capture output compares do not occur 12 2 4 Timer Interrupt Enable Register TI...

Page 345: ...art request generation Bit 6 Reserved This bit is reserved It always reads as 0 and cannot be modified Bit 5 Underflow Interrupt Enable TCIEU Enables or disables interrupt requests when the underflow flag TCFU of the channel 1 2 timer status register TSR is set to 1 This bit is reserved for channels 0 3 and 4 It always reads as 0 The write value should always be 1 Bit 5 TCIEU Description 0 Disable...

Page 346: ...nnels 1 and 2 It always reads as 1 The write value should always be 1 Bit 2 TGIEC Description 0 Disable interrupt requests TGIC due to the TGFC bit initial value 1 Enable interrupt requests TGIC due to the TGFC bit Bit 1 TGR Interrupt Enable B TGIEB Enables or disables TGFB interrupt requests when the TGFB bit of the TSR register is set to 1 Bit 1 TGIEB Description 0 Disable interrupt requests TGI...

Page 347: ...t 7 6 5 4 3 2 1 0 TCFD TCFU TCFV TGFB TGFA Initial value 1 1 0 0 0 0 0 0 R W R R R W R W R R R W R W Note Only 0 writes to clear the flags are possible Channels 3 4 TSR3 TSR4 Bit 7 6 5 4 3 2 1 0 TCFD TCFV TGFD TGFC TGFB TGFA Initial value 1 1 0 0 0 0 0 0 R W R R R R W R W R W R W R W Note Only 0 writes to clear the flags are possible Bit 7 Count Direction Flag TCFD This status flag indicates the c...

Page 348: ...en the TCNT value overflows H FFFF H 0000 2 Notes 1 For channel 4 this flag is cleared by DTC transfer due to TCFV 2 For channel 4 this flag is also set when the TCNT value underflows H 0001 H 0000 in complementary PWM mode Bit 3 Input Capture Output Compare Flag D TGFD This status flag indicates the occurrence of a channel 0 3 or 4 TGRD register input capture or compare match This bit is reserved...

Page 349: ...tes the occurrence of a TGRB register input capture or compare match Bit 1 TGFB Description 0 Clear condition With TGFB 1 a 0 write to TGFB following a read Cleared by DTC transfer due to TGFB initial value 1 Set conditions When TGRB is functioning as an output compare register TCNT TGRB When TGRB is functioning as input capture the TCNT value is sent to TGRB by the input capture signal Bit 0 Inpu...

Page 350: ...ment counter 1 2 TCNT2 Increment decrement counter 1 3 TCNT3 Increment decrement counter 2 4 TCNT4 Increment decrement counter 2 Notes 1 Can only be used as an increment decrement counter in phase counting mode with other channel overflow underflow counting It becomes an increment counter in all other cases 2 Can only be used as an increment counter in complementary PWM mode It becomes an incremen...

Page 351: ...its is disabled they may only be accessed in 16 bit units Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W 12 2 8 Timer Start Register TSTR The timer start register TSTR is an 8 bit read write register that starts and stops the timer counters TCNT of channels 0 4 TSTR is...

Page 352: ...hro Register TSYR The timer synchro register TSYR is an 8 bit read write register that selects independent or synchronous TCNT counter operation for channels 0 4 Channels for which 1 is set in the corresponding bit will be synchronized TSYR is initialized to H 00 upon power on reset or standby mode Manual reset does not initialize TSYR Bit 7 6 5 4 3 2 1 0 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial valu...

Page 353: ...C bit in order to have clear synchronization Bits 5 3 Reserved These bits always read as 0 The write value should always be 0 12 2 10 Timer Output Master Enable Register TOER The timer output master enable register TOER enables disables output settings for output pins TIOC4D TIOC4C TIOC3D TIOC4B TIOC4A and TIOC3B These pins do not output correctly if the TOER bits have not been set Set TOER of CH3...

Page 354: ...ut Bit 3 OE3D Description 0 Disable TIOC3D pin MTU output initial value 1 Enable TIOC3D pin MTU output Bit 2 Master Enable TIOC4B OE4B Enables or disables the TIOC4B pin MTU output Bit 2 OE4B Description 0 Disable TIOC4B pin MTU output initial value 1 Enable TIOC4B pin MTU output Bit 1 Master Enable TIOC4A OE4A Enables or disables the TIOC4A pin MTU output Bit 1 OE4A Description 0 Disable TIOC4A p...

Page 355: ...ed with the PWM period Bit 6 PSYE Description 0 Toggle output synchronous with PWM period disabled initial value 1 Toggle output synchronous with PWM period enabled Bit 1 Output Level Select N OLSN Selects the reverse phase output level of the complementary PWM mode or reset synchronized PWM mode Compare Match Output OLSN Initial Output Active Level Increment Count Decrement Count 0 High level Low...

Page 356: ...e 12 2 12 Timer Gate Control Register TGCR The timer gate control register TGCR is an 8 bit read write register that controls the waveform output necessary for brushless DC motor control in complementary PWM mode reset synchronized PWM mode The TGCR is initialized to H 80 by a power on reset or in the standby mode Manual reset does not initialize TGCR These register settings are ineffective for an...

Page 357: ...chronized PWM output to reverse phase pin output Bit 4 Positive Phase Output P Selects whether to output gate signals directly to the positive phase pin TIOC3B TIOC4A and TIOC4B output or to output by chopping the gate signal and the complementary PWM reset synchronized PWM output Bit 4 P Description 0 Output gate signals directly to positive phase pin output initial value 1 Output chopped gate si...

Page 358: ... Off Off Off Off On 1 0 Off On Off On Off Off 1 Off On Off Off Off On 1 0 0 Off Off On Off On Off 1 On Off Off Off On Off 1 0 Off Off On On Off Off 1 Off Off Off Off Off Off 12 2 13 Timer Subcounter TCNTS The timer subcounter TCNTS is a 16 bit read only counter that is used only in complementary PWM mode The TCNTS counter is initialized to H 00 by a power on reset or in standby mode Manual reset d...

Page 359: ... R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W 12 2 15 Timer Period Data Register TCDR The timer period data register TCDR is a 16 bit register used only in complementary PWM mode Set the PWM carrier sync value as the TCDR register value This register is constantly compared with the TCNTS counter in complementary PWM mode and when...

Page 360: ... Always access in 16 bit units Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W 12 3 Bus Master Interface 12 3 1 16 Bit Registers The timer counters TCNT and general registers TGR are 16 bit registers A 16 bit data bus to the bus master enables 16 bit read writes 8 bit r...

Page 361: ...Upper 8 bits Lower 8 bits Bus master Internal data bus Module data bus Figure 12 4 8 Bit Register Access Operation Bus Master TCR Upper 8 Bits TMDR Bus interface Upper 8 bits Lower 8 bits Bus master Internal data bus Module data bus Figure 12 5 8 Bit Register Access Operation Bus Master TMDR Lower 8 Bits TCR TMDR Bus interface Upper 8 bits Lower 8 bits Bus master Internal data bus Module data bus ...

Page 362: ...ously the value previously stored in the TGR is transferred to the buffer register Cascade Connection Operation The channel 1 and channel 2 counters TCNT1 and TCNT2 can be connected together to operate as a 32 bit counter PWM Mode In PWM mode a PWM waveform is output The output level can be set by the TIOR register Each TGR can be set for PWM waveform output with a duty cycle between 0 and 100 Pha...

Page 363: ...n When a start bit CST0 CST4 in the timer start register TSTR is set to 1 the corresponding timer counter TCNT starts counting There are two counting modes a free running mode and a periodic mode To select the counting operation figure 12 7 1 Set bits TPSC2 TPSC0 in the TCR to select the counter clock At the same time set bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input cloc...

Page 364: ...nning mode When a bit in the TSTR is set to 1 the corresponding timer counter operates as a free running counter and begins to increment When the count overflows from H FFFF H 0000 the TCFV bit in the timer status register TSR is set to 1 If the TCIEV bit in the timer s corresponding timer interrupt enable register TIER is set to 1 the MTU will make an interrupt request to the interrupt controller...

Page 365: ...request to the interrupt controller After the compare match TCNT continues counting from H 0000 Figure 12 9 shows an example of periodic counting CST bit TCNT value Time Counter cleared by TGR compare match TGR H 0000 TGF Flag cleared by software or DTC DMAC activation Figure 12 9 Periodic Counter Operation Compare Match Waveform Output Function The MTU can output 0 level 1 level or toggle output ...

Page 366: ...are match A and 0 is output upon compare match B When the pin level matches the set level the pin level does not change H FFFF H 0000 TIOCA TCNT value Time TGRA TGRB TIOCB Does not change Does not change 1 output Does not change Does not change 0 output Figure 12 11 Example of 0 Output 1 Output Waveform Output Operation Toggle Output Figure 12 12 shows the toggle output In the example the TCNT ope...

Page 367: ...ge falling edge or both edges Channels 0 and 1 can use other channel counter input clocks or compare match signals as input capture sources The procedure for selecting the input capture operation figure 12 13 is 1 Set the TIOR to select the input capture function of the TGR then select the input capture source and rising edge falling edge or both edges as the input edge 2 Set the CST bit in the TS...

Page 368: ... H 0160 H 0005 H 0010 H 0000 TIOCB TIOCA TGRA TGRB H 0005 H 0160 H 0010 H 0180 Time Figure 12 14 Input Capture Operation 12 4 3 Synchronous Operation In the synchronizing mode two or more timer counters can be rewritten simultaneously synchronized preset Multiple timer counters can also be cleared simultaneously using TCR settings synchronized clear The synchronizing mode can increase the number o...

Page 369: ... capture using bits CCLR2 CCLR0 in the TCR 4 Set the counter clear source to synchronized clear using the CCLR2 CCLR0 bits of the TCR 5 Set the CST bits for the corresponding channels in the TSTR to 1 to start counting in the TCNT Select counter clear source Channel that generated clear source No Yes Select synchronizing mode Set synchronizing mode Synchronized preset Set TCNT Start counting Set c...

Page 370: ...onous counter clears by synchronous presets and TGR0B register compare matches Accordingly a three phase PWM waveform with the data set in the TGR0B register as its PWM period is output from the TIOC0A TIOC1A and TIOC2A pins See section 12 4 6 PWM Mode for details on the PWM mode TCNT0 TCNT2 values Time TIOC0A Synchronized clear on TGR0B compare match TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H 0000 TIO...

Page 371: ...re register When TGR Is an Output Compare Register When a compare match occurs the corresponding channel buffer register value is transferred to the general register Figure 12 17 shows an example Compare match signal Buffer register TCNT Comparator General register Figure 12 17 Compare Match Buffer Operation When TGR Is an Input Capture Register When an input capture occurs the timer counter TCNT ...

Page 372: ...tion Setting Procedure Buffer Operation Examples when TGR Is an Output Compare Register Figure 12 20 shows an example of channel 0 set to PWM mode 1 and the TGRA and TGRC registers set for buffer operation The TCNT counter is cleared by a compare match B and the output is a 1 upon compare match A and 0 output upon compare match B Because buffer mode is selected a compare match A changes the output...

Page 373: ...set for buffer operation The TCNT counter is cleared by a TGRA register input capture and the TIOCA pin input capture input edge is selected as both rising and falling edge Because buffer mode is selected an input capture A causes the TCNT counter value to be stored in the TGRA register and the value that was stored in the TGRA up until that time is simultaneously transferred to the TGRC register ...

Page 374: ... 6 shows the cascade connection combinations Table 12 6 Cascade Connection Combinations Combination Upper 16 Bits Lower 16 Bits Channel 1 channel 2 TCNT1 TCNT2 Procedure for Setting Cascade Connection Mode Figure 12 22 1 Set the TPSC2 TPSC 0 bits of the channel 1 timer control register TCR to B 111 to select count by TCNT2 overflow underflow 2 Set the CST bits corresponding to the upper and lower ...

Page 375: ...are match as a counter clear source All five channels can be independently set to PWM mode Synchronous operation is also possible There are two PWM modes PWM mode 1 Generates PWM output using the TGRA and TGRB registers and TGRC and TGRD registers as pairs The initial output values are those established in the TGRA and TGRC registers When the values set in TGR registers being used as a pair are eq...

Page 376: ... setting TGR is not possible in PWM mode 2 Procedure for Selecting the PWM Mode Figure 12 24 1 Set bits TPSC2 TPSC0 in the TCR to select the counter clock source At the same time set bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock 2 Set bits CCLR2 CCLR0 in the TCR to select the TGR to be used as a counter clear source 3 Set the period in the TGR selected in step 2 and...

Page 377: ...ter compare match is used as a TCNT counter clear source the TGRA register initial output value and output compare output value are both 0 and the TGRB register output compare output value is a 1 In this example the value established in the TGRA register becomes the period and the value established in the TGRB register becomes the duty cycle Counter cleared by TGRA compare match TCNT value TGRA TG...

Page 378: ...ished in the TGR1B register becomes the period and the value established in the other TGR register becomes the duty cycle TGR0A TGR0B TGR0C TGR0D TGR1A TGR1B TCNT value Time H 0000 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Counter cleared on TGR1B compare match Figure 12 26 PWM Mode Operation Example Mode 2 0 Duty Cycle Figure 12 27 shows an example of a 0 duty cycle PWM waveform output in PWM mode TGRA ...

Page 379: ...write 100 duty cycle 0 duty cycle TGRB rewrite Figure 12 28 PWM Mode Operation Example 100 Duty Cycle 12 4 7 Phase Counting Mode The phase counting mode detects the phase differential of two external clock inputs and counts the TCNT counter up or down This mode can be set for channels 1 and 2 When set in the phase counting mode an external clock is selected for the counter input clock regardless o...

Page 380: ...register TMDR to select the phase counting mode 2 Set the CST bit of the timer start register TSTR to 1 to start the count Phase counting mode Select phase counting mode Start counting Phase counting mode 1 2 Figure 12 29 Procedure for Selecting the Phase Counting Mode Phase Counting Operation Examples The phase counting mode uses the phase difference between two external clocks to increment decre...

Page 381: ...Table 12 9 Phase Count Mode 1 Up Down Counting Conditions TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation 1 high level Rising edge Increment 0 low level Falling edge Rising edge 0 low level Falling edge 1 high level 1 high level Falling edge Decrement 0 low level Rising edge Rising edge 1 high level Falling edge 0 low level ...

Page 382: ... Table 12 10 Phase Count Mode 2 Up Down Counting Conditions TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation 1 high level Rising edge Does not count don t care 0 low level Falling edge Does not count don t care Rising edge 0 low level Does not count don t care Falling edge 1 high level Increment 1 high level Falling edge Does not count don t care 0 low level Rising edge Do...

Page 383: ... Table 12 11 Phase Count Mode 3 Up Down Counting Conditions TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation 1 high level Rising edge Does not count don t care 0 low level Falling edge Does not count don t care Rising edge 0 low level Does not count don t care Falling edge 1 high level Increment 1 high level Falling edge Decrement 0 low level Rising edge Does not count don...

Page 384: ...evel Rising edge Rising edge 1 high level Does not count don t care Falling edge 0 low level Phase Counting Mode Application Example Figure 12 34 shows an example where channel 1 is set to phase counting mode and is teamed with channel 0 to input a two phase encoder pulse for a servo motor to accurately detect position and speed Channel 1 is set to phase counting mode 1 and the encoder pulse A pha...

Page 385: ... 0 TGR0A and TGR0C register compare match is used as an input capture source and all of the control period increment and decrement values are stored TCLKA TCLKB Edge detection circuit TCNT1 TCNT0 TGR1A speed period capture TGR0A speed control period TGR0C position control period TGR0B pulse width capture TGR0D buffer operation TGR1B position period capture Channel 0 Channel 1 Figure 12 34 Phase Co...

Page 386: ... 3 TIOC4D PWM output 3 negative phase waveform of PWM output 3 Table 12 14 Register Settings for Reset Synchronized PWM Mode Register Description of Contents TCNT3 Initial setting of H 0000 TCNT4 Initial setting of H 0000 TGR3A Set count cycle for TCNT3 TGR3B Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins TGR4A Sets the turning point for PWM waveform output by the TIO...

Page 387: ...nge of TCNT3 X TGR3A X set value With X TGRA cycle duty cycle the output waveform goes into toggle operation at the point where TCNT3 TGR3A X 7 Select enabling disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register TOCR and set the PWM output level with bits OLSP and OLSN 8 Set bits MD3 MD0 in TMDR3 to B 1000 to select the reset synchronized ...

Page 388: ...synchronized PWM mode Brushless DC motor control setting Set TCNT 6 Enable PWM output Set reset synchronized PWM mode 7 PWM cycle output enabling PWM output level setting 9 Start count operation 10 Reset synchronized PWM mode Figure 12 35 Procedure for Selecting the Reset Synchronized PWM Mode ...

Page 389: ... TCNT3 and TGR3A compare match occurs and then begins incrementing from H 0000 The PWM output pin output toggles with each occurrence of a TGR3B TGR4A TGR4B compare match and upon counter clears TGR3A TGR3B TGR4B H 0000 TGR4A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Time TCNT3 and TCNT4 values Figure 12 36 Reset Synchronized PWM Mode Operation Example When the TOCR s OLSN 1 and OLSP 1 ...

Page 390: ... shows the settings of the registers A function to directly cut off the PWM output by using an external signal is supported as a port function Table 12 15 Output Pins for Complementary PWM Mode Channel Output Pin Description 3 TIOC3A Toggle output synchronized with PWM period or I O port TIOC3B PWM output 1 TIOC3C I O port Avoid setting this pin as a timer I O pin in the complementary PWM mode TIO...

Page 391: ...ng TGR4C PWM output 2 TGR4A buffer register Always readable writable TGR4D PWM output 3 TGR4B buffer register Always readable writable Timer dead time data register TDDR Set TCNT4 and TCNT3 offset value dead time value Maskable by BSC BCR1 setting Timer cycle data register TCDR Set TCNT4 upper limit value 1 2 carrier cycle Maskable by BSC BCR1 setting Timer cycle buffer register TCBR TCDR buffer r...

Page 392: ...ator Comparator Match signal Match signal Output controller Output protection circuit PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 POE0 POE1 POE2 POE3 External cutoff input External cutoff interrupt Registers that can always be read or written from the CPU Registers that cannot be read or written from the CPU except for TCNTS which can only be read...

Page 393: ...om another channel during complementary PWM mode operation In this case synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register TSYR 6 Set the output PWM duty in the duty registers TGR3B TGR4A TGR4B and buffer registers TGR3D TGR4C TGR4D Set the same initial value in each corresponding TGR 7 Set the dead time in the dead time register TDDR 1 ...

Page 394: ...ng TCNT setting Inter channel cycle setting TGR setting Dead time carrier cycle setting PWM cycle output enabling PWM output level setting Complementary PWM mode setting 3 Enable waveform output Start count operation Complementary PWM mode 2 4 5 6 7 8 9 10 11 1 Figure 12 38 Example of Complementary PWM Mode Setting Procedure ...

Page 395: ...000 When the CST bit is set to 1 TCNT4 counts up in synchronization with TCNT3 and switches to down counting when it matches TCDR On reaching H 0000 TCNT4 switches to up counting and the operation is repeated in this way TCNTS is a read only counter It need not be initialized When TCNT3 matches TCDR during TCNT3 and TCNT4 up down counting down counting is started and when TCNTS matches TCDR the op...

Page 396: ...mporary register in the Tb interval Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGR3A when counting up or H 0000 when counting down The timing for transfer from the temporary register to ...

Page 397: ...4A Output waveform Output waveform Tb2 Ta Tb1 Ta Tb2 Ta TCNT3 TCNT4 TCNTS Output waveform is active low H 6400 H 0080 H 6400 H 6400 H 0080 H 0080 Transfer from temporary register to compare register Transfer from temporary register to compare register Figure 12 40 Example of Complementary PWM Mode Operation ...

Page 398: ...uiring Initialization Register Counter Set Value TGR3C 1 2 PWM carrier cycle dead time Td TDDR Dead time Td TCBR 1 2 PWM carrier cycle TGR3D TGR4C TGR4D Initial PWM duty value for each phase TCNT4 H 0000 Note The TGR3C set value must be the sum of 1 2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR PWM output level setting In complementary PWM mode the PWM pulse output level is set ...

Page 399: ... The values set in TGR3C and TCBR are transferred simultaneously to TGR3A and TCDR in accordance with the transfer timing selected with bits MD3 MD0 in the timer mode register TMDR The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest and from the current cycle when performed in the trough Figure 12 41 illustrates the operation when the PWM cycle is ...

Page 400: ...er is transferred after TCNTS halts The temporary register value is transferred to the compare register at the data update timing set with bits MD3 MD0 in the timer mode register TMDR Figure 12 42 shows an example of data updating in complementary PWM mode This example shows the mode in which data updating is performed at both the counter crest and trough When rewriting buffer register data a writ...

Page 401: ...ansfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGR3A TGR4C TGR4A H 0000 BR data1 data2 data3 data4 data5 data6 data1 data1 data2 data3 data4 data6 data2 data3 data4 data5 data6 Temp_R GR Time Compare register Buffer register Figure 12 42 Example of Data Update in Complementar...

Page 402: ...re 12 43 shows an example of the initial output in complementary PWM mode An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 12 44 Timer output control register settings OLSN bit 0 initial output high active level low OLSP bit 0 initial output high active level low TCNT3 4 value TGR4A TDDR TCNT3 TCNT4 Initial output Dead time Time Active le...

Page 403: ...SP bit 0 initial output high active level low TCNT3 4 value TGR4A TDDR TCNT3 TCNT4 Initial output Time Active level TCNT3 4 count start TSTR setting Complementary PWM mode TMDR setting Positive phase output Negative phase output Figure 12 44 Example of Initial Output in Complementary PWM Mode 2 ...

Page 404: ...re match c that turns off the positive phase has the highest priority and compare matches occurring prior to c are ignored In normal cases compare matches occur in the order a b c d or c d a b as shown in figure 12 45 If compare matches deviate from the a b c d order since the time for which the negative phase is off is less than twice the dead time the figure shows the positive phase as not being...

Page 405: ... H 0000 Positive phase Negative phase Figure 12 45 Example of Complementary PWM Mode Waveform Output 1 T2 period T1 period T1 period TGR3A TCDR TDDR H 0000 Positive phase Negative phase c d a a b b Figure 12 46 Example of Complementary PWM Mode Waveform Output 2 ...

Page 406: ...00 Positive phase Negative phase Figure 12 47 Example of Complementary PWM Mode Waveform Output 3 a b c d a b T2 period T1 period T1 period TGR3A TCDR TDDR H 0000 Positive phase Negative phase Figure 12 48 Example of Complementary PWM Mode 0 and 100 Waveform Output 1 ...

Page 407: ...se Negative phase a c d a b b Figure 12 49 Example of Complementary PWM Mode 0 and 100 Waveform Output 2 T2 period T1 period T1 period a b c d TGR3A TCDR TDDR H 0000 Positive phase Negative phase Figure 12 50 Example of Complementary PWM Mode 0 and 100 Waveform Output 3 ...

Page 408: ... period T1 period a b c b d a Figure 12 51 Example of Complementary PWM Mode 0 and 100 Waveform Output 4 c a d b T2 period T1 period T1 period TGR3A TCDR TDDR H 0000 Positive phase Negative phase Figure 12 52 Example of Complementary PWM Mode 0 and 100 Waveform Output 5 ...

Page 409: ...re match and turn off compare match for the same phase occur simultaneously both compare matches are ignored and the waveform does not change Toggle output synchronized with PWM cycle In complementary PWM mode toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register TOCR An example of a toggle output waveform is ...

Page 410: ...er control register TCR it is possible to have TCNT3 TCNT4 and TCNTS cleared by another channel Figure 12 54 illustrates the operation Use of this function enables counter clearing and restarting to be performed by means of an external signal TGR3A TCDR TDDR H 0000 Channel 1 input capture A TCNT1 TCNT3 TCNT4 TCNTS Synchronous counter clearing by channel 1 input capture A Figure 12 54 Counter Clear...

Page 411: ...he output on off state is switched when the UF VF or WF bit in TGCR is cleared to 0 or set to 1 The drive waveforms are output from the complementary PWM mode 6 phase output pins With this 6 phase output in the case of on output it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1 When the N bit or P bit is 0 level output is selected Th...

Page 412: ... N 1 P 1 FB 0 output active level high Figure 12 56 Example of Output Phase Switching by External Input 2 TGCR UF bit VF bit WF bit TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6 phase output When BDC 1 N 0 P 0 FB 0 output active level high Figure 12 57 Example of Output Phase Switching by Means of UF VF WF Bit Settings 1 ...

Page 413: ...ttings 2 A D conversion start request setting In complementary PWM mode an A D conversion start request can be issued using a TGR3A compare match or a compare match on a channel other than channels 3 and 4 When start requests using a TGR3A compare match are set A D conversion can be started at the center of the PWM pulse A D conversion start requests can be set by setting the TTGE bit to 1 in the ...

Page 414: ...n table 12 3 This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers control registers and counters Halting of PWM output by external signal The 6 phase PWM output pins can be set automatically to the high impedance state by inputting specified external signals There are four external signal input pins See section 12 9 Port Output Enable PO...

Page 415: ...interrupt sources Input Capture Compare Match Interrupts If the TGIE bit of the timer input enable register TIER is already set to 1 when the TGF flag in the timer status register TSR is set to 1 by a TGR register input capture compare match of any channel an interrupt request is sent to the interrupt controller The interrupt request is canceled by clearing the TGF flag to 0 The MTU has 16 input c...

Page 416: ...nput capture compare match Yes Yes TGI2B TGR2B input capture compare match No Yes TCI2V TCNT2 overflow No No TCI2U TCNT2 underflow No No 3 TGI3A TGR3A input capture compare match Yes Yes TGI3B TGR3B input capture compare match No Yes TGI3C TGR3C input capture compare match No Yes TGI3D TGR3D input capture compare match No Yes TCI3V TCNT3 overflow No No 4 TGI4A TGR4A input capture compare match Yes...

Page 417: ... Direct Memory Access Controller DMAC The MTU has 5 TGRA register input capture compare match interrupts one for any channel that can be used as DMAC activation sources 12 5 3 A D Converter Activation The TGRA register input capture compare match of any channel can be used to activate the on chip A D converter If the TTGE bit of the TIER is already set to 1 when the TGFA flag in the TSR is set to ...

Page 418: ...n in figure 12 60 and figure 12 61 shows count timing with external clock operation phase counting mode TCNT input clock Internal clock TCNT φ Falling edge Falling edge Rising edge N 1 N N 1 N 2 Figure 12 59 TCNT Count Timing during Internal Clock Operation TCNT input clock External clock TCNT φ Falling edge Falling edge Rising edge N 1 N N 1 N 2 Figure 12 60 TCNT Count Timing during External Cloc...

Page 419: ...s issued the output value set in TIOR or TOCR is output to the output compare output pin TIOC pin After TCNT and TGR matching a compare match signal is not issued until immediately before the TCNT input clock Output compare output timing normal mode and PWM mode is shown in figure 12 62 See figure 12 63 for output compare output timing in complementary PWM mode and reset sync PWM mode TCNT input c...

Page 420: ...Output Compare Output Timing Complementary PWM Mode Reset Sync PWM Mode Input Capture Signal Timing Figure 12 64 illustrates input capture timing Input capture input Input capture signal TCNT TGR φ N N 2 N N 2 N 1 Rising edge Falling edge Figure 12 64 Input Capture Input Signal Timing ...

Page 421: ...wn in figure 12 65 Figure 12 66 shows the timing for counter clearing due to input capture Compare match signal φ Counter clear signal TCNT TGR N N H 0000 Figure 12 65 Counter Clearing Timing Compare Match Input capture signal φ Counter clear signal TCNT TGR N N H 0000 Figure 12 66 Counter Clearing Timing Input Capture ...

Page 422: ... capture buffer operation timing TCNT φ Compare match buffer signal TGRA TGRB TGRC TGRD n n 1 n N N Compare match signal Figure 12 67 Buffer Operation Timing Compare Match TCNT φ Input capture signal buffer TGRA TGRB TGRC TGRD N N 1 n N n N 1 N Input capture signal Figure 12 68 Buffer Operation Timing Input Capture ...

Page 423: ...e match as well as TGI interrupt request signal timing Compare match signal TCNT TCNT input clock φ TGR TGF flag TGI interrupt N N 1 N Figure 12 69 TGI Interrupt Timing Compare Match Setting TGF Flag Timing during Input Capture Figure 12 70 shows timing for the TGF flag of the timer status register TSR due to input capture as well as TGI interrupt request signal timing ...

Page 424: ...as well as TCIV interrupt request signal timing Figure 12 72 shows timing for the TCFU flag of the timer status register TSR due to underflow as well as TCIU interrupt request signal timing Figure 12 73 shows timing for the TCFV flag of TSR4 due to underflow in complementary PWM mode as well as TCIV interrupt request signal timing Overflow signal TCNT underflow TCNT input clock φ TCFV flag TCIV in...

Page 425: ...k φ TCFU flag TCIU interrupt H 0000 H FFFF Figure 12 72 TCIU Interrupt Setting Timing Underflow signal TCNT underflow TCNT input clock φ TCFV flag TCIV interrupt H 0000 H 0001 H 0001 Figure 12 73 TCIV Interrupt Setting Timing TSR4 Complementary PWM Mode ...

Page 426: ...aring by the CPU Figure 12 75 shows timing for clearing due to the DTC DMA controller Status flag Interrupt request signal Address Write signal φ T1 T2 TSR write cycle TSR address Figure 12 74 Timing of Status Flag Clearing by the CPU Status flag Interrupt request signal Address φ T1 T2 DTC DMAC read cycle DTC DMAC write cycle Source address Destination address T1 T2 Figure 12 75 Timing of Status ...

Page 427: ...tes or greater Input clock conditions for phase counting mode are shown in figure 12 76 Overlap Phase difference Overlap Phase difference Pulse width Pulse width Pulse width Pulse width TCLKB TCLKD TCLKA TCLKC Note Phase difference and overlap 1 5 states or greater Pulse width 2 5 states or greater Figure 12 76 Phase Difference Overlap and Pulse Width in Phase Count Mode 12 7 2 Note on Cycle Setti...

Page 428: ...signal is issued in the T2 state during the TCNT write cycle TCNT clearing has priority and TCNT write is not conducted figure 12 77 Counter clear signal TCNT Address Write signal φ T1 T2 TCNT write cycle TCNT address N H 0000 Figure 12 77 TCNT Write and Clear Contention ...

Page 429: ... is issued in the T2 state during the TCNT write cycle TCNT write has priority and the counter is not incremented figure 12 78 TCNT input clock TCNT Address Write signal φ T1 T2 TCNT write cycle TCNT write data TCNT address M N Figure 12 78 TCNT Write and Increment Contention ...

Page 430: ... the TGR Data to be transferred differs depending on channels 0 and 3 and 4 data on channel 0 is that after write and on channels 3 and 4 before write figures 12 79 and 12 80 Buffer register Compare match signal Compare match buffer signal Address Write signal TGR φ T1 T2 TGR write cycle Buffer register address N M Buffer register write data M Figure 12 79 TGR Write and Compare Match Contention Ch...

Page 431: ...ompare match buffer signal TGR Address Write signal φ T1 T2 TGR write cycle Buffer register address N N M Compare match signal Buffer register write data Figure 12 80 TGR Write and Compare Match Contention Channels 3 and 4 ...

Page 432: ...re signal is issued in the T1 state of the TGR read cycle the read data is that after input capture transfer figure 12 81 TGR Input capture signal Internal data bus Address Read signal φ T1 T2 TGR read cycle TGR address M X M Figure 12 81 TGR Read and Input Capture Contention ...

Page 433: ...apture signal is issued in the T2 state of the TGR read cycle input capture has priority and TGR write does not occur figure 12 82 TGR Input capture signal TCNT Address Write signal φ T1 T2 TGR write cycle TGR address M M Figure 12 82 TGR Write and Input Capture Contention ...

Page 434: ...ate of the buffer write cycle write to the buffer register does not occur and buffer operation takes priority figure 12 83 TGR Input capture signal TCNT Address Write signal Buffer register φ T1 T2 Buffer register write cycle Buffer register address N M N M Figure 12 83 Buffer Register Write and Input Capture Contention ...

Page 435: ...12 7 10 TCNT2 Write and Overflow Underflow Contention in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection when a contention occurs during TCNT1 count during a TCNT2 overflow underflow in the T2 state of the TCNT2 write cycle the write to TCNT2 is conducted and the TCNT1 count signal is prohibited At this point if there is match with TGR1A or TGR1B and the TCNT1 value ...

Page 436: ...NT write cycle φ Address Write signal TCNT2 TGR2A B Ch2 compare match signal A B TCNT1 input clock TCNT1 TGR1A Ch1 compare match signal A TGR1B Ch1 inputcapture signal B TCNT0 TGR0A D Ch0 input capture signal A D Figure 12 85 TCNT2 Write and Overflow Underflow Contention with Cascade Connection ...

Page 437: ...lementary PWM mode operation Counter operation stop Complementary PMW restart Figure 12 86 Counter Value during Complementary PWM Mode Stop 12 7 12 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode conduct rewrites by buffer operation for the PWM cycle setting register TGR3A PWM carrier cycle setting register TCDR and duty setting registers TGR3B TRG4A and TGR4B In compl...

Page 438: ...as the buffer register for TRG4A When setting buffer operation for reset sync PWM mode take particular care since compare match flag TGFC bit and TGFD bit operations differ with TSR3 and TSR4 The TGFC bit and TGFD bit of TSR3 are not set when TGR3C and TGR3D are operating as buffer registers On the other hand TSR4 s TGFC and TGFD bits are set even when TGR4C and TGR4D are operating as buffer regis...

Page 439: ...in will be unable to produce its waveform output if the BFA bit of TMDR4 is set to 1 In reset sync PWM mode the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR3 For example if the BFA bit of TMDR3 is set to 1 TGR3C functions as the buffer register for TGR3A At the same time TGR4C functions as the buffer register for TRG4A When setting buffer operatio...

Page 440: ...D TCNT3 TGR3A TGR3C TGR3B TGR3D TGR4A TGR4C TGR4B TGR4D Not set Not set Not set Buffer transfer with compare match A3 Point a Point b Not set Figure 12 88 Buffer Operation and Compare Match Flags in Reset Sync PWM Mode for A Mask 12 7 14 Overflow Flags in Reset Sync PWM Mode When set to reset sync PWM mode TCNT3 and TCNT4 start counting when the CST3 bit of TSTR is set to 1 At this point TCNT4 s c...

Page 441: ...d by compare match A3 Not set Set Figure 12 89 Reset Sync PWM Mode Overflow Flag A mask operation For A mask the above operation is modified as follows When set to reset sync PWM mode TCNT3 and TCNT4 start counting when the CST3 bit of TSTR is set to 1 At this point TCNT4 s count clock source and count edge obey the TCR3 setting In reset sync PWM mode with cycle register TGR3A s set value at H FFF...

Page 442: ...404 TGR3A H FFFF H 0000 TCF3V TCF4V TCNT3 TCNT4 Not set Not set Counter clear by compare match 3A Figure 12 90 Reset Sync PWM Mode Overflow Flag for A Mask ...

Page 443: ...a description when TGR3B is the specified duty setting register TGR3D the buffer register with TGR3A Td as the buffer register set value TGR3A TCDR TGR3A Td TGR3B TDDR H 0000 TIOC3A TIOC3B TIOC3D TGF3B setting signal TGF3D setting signal TCNT3 TGR3D TCNT4 TGR3B TGR3D Point a Point b Point c Point d Point a TGR3D setting Td Point b TGR3D setting TGR3A Td or TGR3A 2TD Point c TGR3D setting Td or 2Td...

Page 444: ...92 shows an example when setting the duty setting register to TGR3B buffer register to TGR3D and Buffer register to TGR3A Td TGR3A TCDR TGR3A Td TGR3B TDDR H 0000 TIOC3A TIOC3B TIOC3D Point a Point b Point c Point d TGF3B setting signal TGF3D setting signal TCNT3 TGR3D TCNT4 TGR3B TGR3D Set signals are output when Point a TGR3D setting is Td Point b TGR3D settings are TGR3A Td TGR3A 2Td Point c TG...

Page 445: ...CFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 12 93 shows the operation timing when a TGR compare match is specified as the clearing source and H FFFF is set in TGR φ TCNT input clock TCNT Counter clear signal TGF flag TCFV flag H FFFF H 0000 Disabled Figure 12 93 Contention between Overflow and Counter Clearing ...

Page 446: ...le and overflow underflow occurs the TCNT write takes precedence and the TCFV TCFU flag in TSR is not set Figure 12 94 shows the operation timing in this case φ Address Write signal TCNT input clock TCNT TCFV flag H FFFF N TCNT write data Disabled TCNT write cycle T1 T2 TCNT address Figure 12 94 Contention between TCNT Write and Overflow ...

Page 447: ...reset synchronous PWM mode the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register TOCR In the case of complementary PWM mode or reset synchronous PWM mode TIOR should be set to H 00 12 7 20 Cautions on Using the Chopping Function in Complementary PWM Mode or Reset Synchronous PWM Mode A Mask Excluded When channels 3 and 4 are in complementary PWM mode...

Page 448: ...e crest trough in the complementary PWM transfer mode set the value following the next value of the PWM duty write to TGR4D while the temporary register is not executing comparisons Furthermore set the occurrence timing of sync clear while the temporary register is not executing comparisons When selecting the mode to transfer using the crest in the transfer mode set the value following the next va...

Page 449: ...entary PWM mode channels 3 and 4 Reset synchronous PWM mode channels 3 and 4 The MTU output pin initialization method for each of these modes is described in this section 12 8 2 Reset Start Operation The MTU output pins TIOC are initialized low by a reset and in standby mode Since MTU pin function selection is performed by the pin function controller PFC when the PFC is set the MTU pin states at t...

Page 450: ...own in table 12 18 Table 12 18 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal 1 2 3 4 5 6 PWM1 7 8 9 10 11 12 PWM2 13 14 15 16 None None PCM 17 18 19 20 None None CPWM 21 22 None None 23 24 RPWM 25 26 None None 27 28 Legend Normal Normal mode PWM1 PWM mode 1 PWM2 PWM mode 2 PCM Phase counting modes 1 4 CPWM Complementary PWM mode RPWM Reset synchronous PWM mode The...

Page 451: ...RC pin To initialize the TGRC pin clear buffer mode carry out initialization then set buffer mode again When making a transition to a mode CPWM RPWM in which the pin output level is selected by the timer output control register TOCR setting switch to normal mode and perform initialization with TIOR then restore TIOR to its initial value and temporarily disable channel 3 and 4 output with the timer...

Page 452: ...overy in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 After a reset the TMDR setting is for normal mode 3 For channels 3 and 4 enable output with TOER before initializing the pins with TIOR 4 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence 5 Set MTU output with the PFC 6 The count operation...

Page 453: ...Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 12 97 Error Occurrence in Normal Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 12 96 11 Set PWM mode 1 12 Initialize the pins with TIOR In PWM mode 1 the TIOC B side is not initialized If initiali...

Page 454: ...1 init 0 out 13 PFC MTU 14 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized cycle register n 0 to 15 High Z High Z Figure 12 98 Error Occurrence in Normal Mode Recovery in PWM Mode 2 1 to 10 are the same as in figure 12 96 11 Set PWM mode 2 12 Initialize the pins with TIOR In PWM mode 2 the cycle register pins are not initialized If initialization is required initialize in norma...

Page 455: ... out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PCM 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 12 99 Error Occurrence in Normal Mode Recovery in Phase Counting Mode 1 to 10 are the same as in figure 12 96 11 Set phase counting mode 12 Initialize the pins with TIOR 13 Set MTU output with the PFC 14 Operatio...

Page 456: ...MDR CPWM 16 TOER 1 17 PFC MTU 18 TSTR 1 MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 12 100 Error Occurrence in Normal Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12 96 11 Initialize the normal mode waveform generation section with TIOR 12 Disable operation of the normal mode waveform generation section with TIOR 13 Disable chan...

Page 457: ...rror occurs 9 PFC PORT 10 TSTR 0 11 TIOR 0 init 0 out 12 TIOR disabled 13 TOER 0 14 TOCR 15 TMDR CPWM 16 TOER 1 17 PFC MTU 18 TSTR 1 MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 12 101 Error Occurrence in Normal Mode Recovery in Reset Synchronous PWM Mode 1 to 13 are the same as in figure 12 100 14 Select the reset synchronous PWM output level and cyclic out...

Page 458: ...in PWM Mode 1 Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Set PWM mode 1 3 For channels 3 and 4 enable output with TOER before initializing the pins with TIOR 4 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence In PWM mode 1 the TIOC B side is not initialized 5 Set MTU output wit...

Page 459: ... 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized TIOC B n 0 to 15 High Z High Z Figure 12 103 Error Occurrence in PWM Mode 1 Recovery in PWM Mode 1 1 to 10 are the same as in figure 12 102 11 Not necessary when restarting in PWM mode 1 12 Initialize the pins with...

Page 460: ...STR 0 11 TMDR PWM2 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized cycle register n 0 to 15 High Z High Z Figure 12 104 Error Occurrence in PWM Mode 1 Recovery in PWM Mode 2 1 to 10 are the same as in figure 12 102 11 Set PWM mode 2 12 Initialize the pins with TIOR In PWM mode 2 the cycle register pins are not initialize...

Page 461: ... 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PCM 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 12 105 Error Occurrence in PWM Mode 1 Recovery in Phase Counting Mode 1 to 10 are the same as in figure 12 102 11 Set phase counting mode 12 Initialize the pins with TIOR 13 Set MTU output with the PFC ...

Page 462: ...TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 12 106 Error Occurrence in PWM Mode 1 Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12 102 11 Set normal mode for initialization of the normal mode waveform generation section 12 Initialize the PWM mode 1 waveform generation section with TIOR 13 Disable operation ...

Page 463: ... 11 TMDR normal 12 TIOR 0 init 0 out 13 TIOR disabled 14 TOER 0 15 TOCR 16 TMDR RPWM 17 TOER 1 18 PFC MTU 19 TSTR 1 MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 12 107 Error Occurrence in PWM Mode 1 Recovery in Reset Synchronous PWM Mode 1 to 14 are the same as in figure 12 106 15 Select the reset synchronous PWM...

Page 464: ...Error Occurrence in PWM Mode 2 Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Set PWM mode 2 3 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence In PWM mode 2 the cycle register pins are not initialized In the example TIOC A is the cycle register 4 Set MTU output with the PFC 5 The ...

Page 465: ...4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM1 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized cycle register n 0 to 15 High Z High Z Figure 12 109 Error Occurrence in PWM Mode 2 Recovery in PWM Mode 1 1 to 9 are the same as in figure 12 108 10 Set PWM mode 1 11 Initialize the pins with TIOR In PWM mod...

Page 466: ...or occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM2 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized cycle register Not initialized cycle register n 0 to 15 High Z High Z Figure 12 110 Error Occurrence in PWM Mode 2 Recovery in PWM Mode 2 1 to 9 are the same as in figure 12 108 10 Not necessary when restarting in PWM mode 2 11 Initialize the pins with T...

Page 467: ...DR PWM2 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PCM 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized cycle register n 0 to 15 High Z High Z Figure 12 111 Error Occurrence in PWM Mode 2 Recovery in Phase Counting Mode 1 to 9 are the same as in figure 12 108 10 Set phase counting mode 11 Initializ...

Page 468: ...o 15 High Z High Z Figure 12 112 Error Occurrence in Phase Counting Mode Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Set phase counting mode 3 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence 4 Set MTU output with the PFC 5 The count operation is started by TSTR 6 Output goes lo...

Page 469: ...init 0 out 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM1 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 12 113 Error Occurrence in Phase Counting Mode Recovery in PWM Mode 1 1 to 9 are the same as in figure 12 112 10 Set PWM mode 1 11 Initialize the pins with TIOR In PWM mode ...

Page 470: ...t 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM2 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Not initialized cycle register Figure 12 114 Error Occurrence in Phase Counting Mode Recovery in PWM Mode 2 1 to 9 are the same as in figure 12 112 10 Set PWM mode 2 11 Initialize the pins with TIOR In PWM mode 2...

Page 471: ...T 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PCM 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 MTU output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 12 115 Error Occurrence in Phase Counting Mode Recovery in Phase Counting Mode 1 to 9 are the same as in figure 12 112 10 Not necessary when restarting in phase counting mode ...

Page 472: ...plementary PWM Mode Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Select the complementary PWM output level and cyclic output enabling disabling with TOCR 3 Set complementary PWM 4 Enable channel 3 and 4 output with TOER 5 Set MTU output with the PFC 6 The count operation is started by TSTR 7 The complementary PWM waveform is output on compar...

Page 473: ... 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 12 117 Error Occurrence in Complementary PWM Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 12 116 11 Set PWM mode 1 MTU output goes low 12 Initialize t...

Page 474: ...he cycle and duty settings at the time the counter was stopped 1 RESET 2 TOCR 3 TMDR CPWM 5 PFC MTU 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 PFC MTU 12 TSTR 1 13 Match MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 12 118 Error Occurrence in Complementary PWM Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12 1...

Page 475: ...ccurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TOER 0 13 TOCR 14 TMDR CPWM 15 TOER 1 16 PFC MTU 17 TSTR 1 MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 12 119 Error Occurrence in Complementary PWM Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12 116 11 Set normal mode and make new settings MTU output goes low 12 Disable channel 3 and...

Page 476: ...rmal 12 TOER 0 13 TOCR 14 TMDR RPWM 15 TOER 1 16 PFC MTU 17 TSTR 1 MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 12 120 Error Occurrence in Complementary PWM Mode Recovery in Reset Synchronous PWM Mode 1 to 10 are the same as in figure 12 116 11 Set normal mode MTU output goes low 12 Disable channel 3 and 4 output with TOER 13 Select the reset synchronous PWM...

Page 477: ...n Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Select the reset synchronous PWM output level and cyclic output enabling disabling with TOCR 3 Set reset synchronous PWM 4 Enable channel 3 and 4 output with TOER 5 Set MTU output with the PFC 6 The count operation is started by TSTR 7 The reset synchronous PWM waveform is output on compare match occurrence...

Page 478: ...urs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 12 122 Error Occurrence in Reset Synchronous PWM Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 12 121 11 Set PWM mode 1 MTU positive phase output is low and negative phase o...

Page 479: ...PORT 10 TSTR 0 11 TOER 0 12 TOCR 13 TMDR CPWM 14 TOER 1 15 PFC MTU 16 TSTR 1 MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 12 123 Error Occurrence in Reset Synchronous PWM Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12 121 11 Disable channel 3 and 4 output with TOER 12 Select the complementary PWM output level and cyclic output e...

Page 480: ...ting 1 RESET 2 TOCR 3 TMDR RPWM 5 PFC MTU 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 PFC MTU 12 TSTR 1 13 Match MTU output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z High Z High Z High Z Figure 12 124 Error Occurrence in Reset Synchronous PWM Mode Recovery in Reset Synchronous PWM Mode 1 to 10 are the same as in figure 12 121 11 Set MTU output with the...

Page 481: ...unctions are selected in cases such as when the oscillator stops or in standby mode Refer to section 4 Clock Pulse Generator CPG for details 12 9 1 Features Each of the POE0 POE3 input pins can be set for falling edge φ 8 16 φ 16 16 or φ 128 16 low level sampling High current pins can be set to high impedance state by POE0 POE3 pin falling edge or low level sampling High current pins can be set to...

Page 482: ...OC4A TIOC4C TIOC4B TIOC4D POE3 POE2 POE1 POE0 Output level detection circuit Output level detection circuit Output level detection circuit Input level detection circuit Falling edge detection circuit Low level detection circuit OCSR ICSR φ 8 φ 16 φ 128 High impedance request control signal Interrupt request Note Includes multiplexed pins Figure 12 125 POE Block Diagram ...

Page 483: ... PE13 TIOC4B MRES and PE15 TIOC4D DACK1 IRQOUT Output All high current pins are made high impedance state when the pins simultaneously output low level for longer than 1 cycle 12 9 4 Register Configuration The POE has the two registers shown in table 12 20 The input level control status register ICSR controls both POE0 POE3 pin input signal detection and interrupts The output level control status ...

Page 484: ... 0 0 0 R W R W R W R W R W R R R R W Bit 7 6 5 4 3 2 1 0 POE3M1 POE3M0 POE2M1 POE2M0 POE1M1 POE1M0 POE0M1 POE0M0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note Only 0 writes are possible to clear the flags Bit 15 POE3 Flag POE3F This flag indicates that a high impedance request has been input to the POE3 pin Bit 15 POE3F Description 0 Clear condition By writing 0 to POE3F a...

Page 485: ...9 Reserved These bits always read as 0 The write value should always be 0 Bit 8 Port Interrupt Enable PIE Enables or disables interrupt requests when any of the POE0F POE3F bits of the ICSR are set to 1 Bit 8 PIE Description 0 Interrupt requests disabled initial value 1 Interrupt requests enabled Bits 7 and 6 POE3 Mode 1 0 POE3M1 and POE3M0 These bits select the input mode of the POE3 pin Bit 7 PO...

Page 486: ...t request on falling edge of POE1 input initial value 1 Accept request when POE1 input has been sampled for 16 φ 8 clock pulses and all are low level 1 0 Accept request when POE1 input has been sampled for 16 φ 16 clock pulses and all are low level 1 Accept request when POE1 input has been sampled for 16 φ 128 clock pulses and all are low level Bits 1 and 0 POE0 Mode 1 0 POE0M1 and POE0M0 These bi...

Page 487: ... maintained Bit 15 14 13 12 11 10 9 8 OSF OCE OIE Initial value 0 0 0 0 0 0 0 0 R W R W R R R R R R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Note Only 0 writes are possible to clear the flag Bit 15 Output Short Flag OSF This flag indicates that among the three pairs of 2 phase outputs compared the outputs of at least one pair have simultaneously become Low level ...

Page 488: ...uest will not be issued even if OSF is set to 1 Therefore in order to have a high impedance request issued according to the result of the output comparison the OIE bit must be set to 1 When OCE 1 and OIE 1 an interrupt request will be generated at the same time as the high impedance request however this interrupt can be masked by means of an interrupt controller INTC setting Bit 9 OCE Description ...

Page 489: ...e sampled with the sampling clock established by the ICSR If even one high level is detected during this interval the low level is not accepted CK Sampling clock 3 POE input PE9 TIOC3B When low level is sampled at all points When high level is sampled at least once Flag set POE received Flag not set High impedance state Note Other large current pins PE11 TIOC3D PE12 TIOC4A PE13 TIOC4B MRES PE14 TI...

Page 490: ...em to their initial state with a power on reset or by clearing all of the bit 12 15 POE0F POE3F flags of the ICSR High current pins that have become high impedance due to output level detection can be released either by returning them to their initial state with a power on reset or by first clearing bit 9 OCE of the OCSR to disable output level compares then clearing the bit 15 OSF flag However wh...

Page 491: ...ansition edge detected High impedance state Note Other high current pins PE11 TICO3D PE12 TIOC4A PE13 TIOC4B MRES PE14 TIOC4C DACK0 AH PE15 TIOC4D DACK1 IRQOUT will enter the high impedance state with the same timing Figure 12 128 Last Transition Edge Detection Operation 12 11 5 Usage Notes To perform POE level detection first set POE input to high level ...

Page 492: ...454 ...

Page 493: ...imer operation an interval timer interrupt is generated at each counter overflow The WDT is also used in recovering from the standby mode 13 1 1 Features Works in watchdog timer mode or interval timer mode Outputs WDTOVF in the watchdog timer mode When the counter overflows in the watchdog timer mode overflow signal WDTOVF is output externally You can select whether to reset the chip internally wh...

Page 494: ... register TCNT TCSR Module bus Bus interface Internal data bus ITI interrupt signal WDTOVF Internal reset signal WDT Note The internal reset signal can be generated by setting the register The type of reset can be selected power on or manual Figure 13 1 WDT Block Diagram 13 1 3 Pin Configuration Table 13 1 shows the pin configuration Table 13 1 Pin Configuration Pin Abbreviation I O Function Watch...

Page 495: ...upcounter The TCNT differs from other registers in that it is more difficult to write to See section 13 2 4 Register Access for details When the timer enable bit TME in the timer control status register TCSR is set to 1 the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 0 CKS2 CKS0 in the TCSR When the value of the TCNT overflows changes from H F...

Page 496: ...R R W R W R W Bit 7 Overflow Flag OVF Indicates that the TCNT has overflowed from H FF to H 00 in the interval timer mode It is not set in the watchdog timer mode Bit 7 OVF Description 0 No overflow of TCNT in interval timer mode initial value Cleared by reading OVF then writing 0 in OVF 1 TCNT overflow in the interval timer mode Bit 6 Timer Mode Select WT IT Selects whether to use the WDT as a wa...

Page 497: ...lock Select 2 0 CKS2 CKS0 These bits select one of eight internal clock sources for input to the TCNT The clock signals are obtained by dividing the frequency of the system clock φ Description Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Clock Source Overflow Interval φ 28 7 MHz 0 0 0 φ 2 initial value 17 9 µs 0 0 1 φ 64 573 4 µs 0 1 0 φ 128 1 1 ms 0 1 1 φ 256 2 3 ms 1 0 0 φ 512 4 6 ms 1 0 1 φ 1024 9 2 ms 1 1...

Page 498: ...clear the flag Bit 7 Watchdog Timer Overflow Flag WOVF Indicates that the TCNT has overflowed H FF H 00 in the watchdog timer mode It is not set in the interval timer mode Bit 7 WOVF Description 0 No TCNT overflow in watchdog timer mode initial value Cleared when software reads WOVF then writes 0 in WOVF 1 Set by TCNT overflow in watchdog timer mode Bit 6 Reset Enable RSTE Selects whether to reset...

Page 499: ... H 5A H FFFF8610 Address Writing to the TCNT 15 8 7 0 Write data H A5 H FFFF8610 Address Writing to the TCSR 15 8 7 0 Write data Figure 13 2 Writing to the TCNT and TCSR Writing to the RSTCSR The RSTCSR must be written by a word access to address H FFFF8612 It cannot be written by byte transfer instructions Procedures for writing 0 in WOVF bit 7 and for writing to RSTE bit 6 and RSTS bit 5 are dif...

Page 500: ...ut if the TCNT fails to be rewritten and overflows occur due to a system crash or the like a WDTOVF signal is output externally figure 13 4 The WDTOVF signal can be used to reset the system The WDTOVF signal is output for 128 φ clock cycles If the RSTE bit in the RSTCSR is set to 1 a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows Either ...

Page 501: ...gnal TCNT value WDTOVF and internal reset generated WOVF 1 WT IT 1 TME 1 WT IT TME Timer mode select bit Timer enable bit H 00 written in TCNT Time 512 φ clocks 128 φ clocks Note Internal reset signal occurs only when the RSTE bit is set to 1 Figure 13 4 Operation in the Watchdog Timer Mode ...

Page 502: ...n to the Standby Mode The TME bit in the TCSR must be cleared to 0 to stop the watchdog timer counter before it enters the standby mode The chip cannot enter the standby mode while the TME bit is set to 1 Set bits CKS2 CKS0 so that the counter overflow interval is equal to or longer than the oscillation settling time See sections 25 3 and 26 3 AC Characteristics for the oscillation settling time R...

Page 503: ... signal OVF Figure 13 6 Timing of Setting the OVF 13 3 5 Timing of Setting the Watchdog Timer Overflow Flag WOVF When the TCNT overflows in the watchdog timer mode the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is output When the RSTE bit is set to 1 TCNT overflow enables an internal reset signal to be generated for the entire chip figure 13 7 H FF H 00 CK TCNT Overflow signal internal...

Page 504: ... T2 T3 TCNT write cycle Figure 13 8 Contention between TCNT Write and Increment 13 4 2 Changing CKS2 CKS0 Bit Values If the values of bits CKS2 CKS0 are altered while the WDT is running the count may increment incorrectly Always stop the watchdog timer by clearing the TME bit to 0 before changing the values of bits CKS2 CKS0 13 4 3 Changing between Watchdog Timer Interval Timer Modes To prevent in...

Page 505: ...tem with the WDTOVF signal use the circuit shown in figure 13 9 Reset input Reset signal to entire system SH7040 Series RES WDTOVF Figure 13 9 Example of a System Reset Circuit with a WDTOVF Signal 13 4 5 Internal Reset with the Watchdog Timer If the RSTE bit is cleared to 0 in the watchdog timer mode the LSI will not reset internally when a TCNT overflow occurs but the TCNT and TCSR in the WDT wi...

Page 506: ...468 ...

Page 507: ...one or two bits Parity even odd or none Multiprocessor bit one or none Receive error detection parity overrun and framing errors Break detection by reading the RxD level directly when a framing error occurs Clocked synchronous mode Serial data communication is synchronized with a clock signal The SCI can communicate with other chips having a clock synchronous communication function There is one se...

Page 508: ... Bus interface Internal data bus RxD RDR TDR RSR TSR SSR SCR SMR BRR φ φ 4 φ 16 φ 64 TEI TxI RxI ERI SCK RSR RDR TSR TDR Receive shift register Receive data register Transmit shift register Transmit data register SMR SCR SSR BRR Serial mode register Serial control register Serial status register Bit rate register TxD SCI Module data bus Figure 14 1 SCI Block Diagram ...

Page 509: ... bit rate and control the transmitter and receiver sections Table 14 2 Registers Channel Name Abbreviation R W Initial Value Address 2 Access Size 0 Serial mode register SMR0 R W H 00 H FFFF81A0 8 16 Bit rate register BRR0 R W H FF H FFFF81A1 8 16 Serial control register SCR0 R W H 00 H FFFF81A2 8 16 Transmit data register TDR0 R W H FF H FFFF81A3 8 16 Serial status register SSR0 R W 1 H 84 H FFFF...

Page 510: ... RDR for storage The RSR is then ready to receive the next data This double buffering allows the SCI to receive data continuously The CPU can read but not write the RDR The RDR is initialized to H 00 by a power on reset or in standby mode Manual reset does not initialize RDR Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R 14 2 3 Transmit Shift Register TSR The transmit shift ...

Page 511: ...CPU can always read and write the TDR The TDR is initialized to H FF by a power on reset or in standby mode Manual reset does not initialize TDR Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W 14 2 5 Serial Mode Register SMR The serial mode register SMR is an 8 bit register that specifies the SCI serial communication format and selects the clock source for the...

Page 512: ...even or odd parity bit is added to transmit data depending on the parity mode O E setting Receive data parity is checked according to the even odd O E mode setting Bit 4 Parity Mode O E Selects even or odd parity when parity bits are added and checked The O E setting is used only in asynchronous mode and only when the parity enable bit PE is set to 1 to enable parity addition and check The O E set...

Page 513: ...ch transmitted character Bit 2 Multiprocessor Mode MP Selects multiprocessor format When multiprocessor format is selected settings of the parity enable PE and parity mode O E bits are ignored The MP bit setting is used only in the asynchronous mode it is ignored in the clock synchronous mode For the multiprocessor communication function see section 14 3 3 Multiprocessor Communication Bit 2 MP Des...

Page 514: ... TIE Description 0 Transmit data empty interrupt request TxI is disabled initial value The TxI interrupt request can be cleared by reading TDRE after it has been set to 1 then clearing TDRE to 0 or by clearing TIE to 0 1 Transmit data empty interrupt request TxI is enabled Bit 6 Receive Interrupt Enable RIE Enables or disables the receive data full interrupt RxI requested when the receive data reg...

Page 515: ...nables or disables multiprocessor interrupts The MPIE setting is used only in the asynchronous mode and only if the multiprocessor mode bit MP in the serial mode register SMR is set to 1 during reception The MPIE setting is ignored in the clock synchronous mode or when the MP bit is cleared to 0 Bit 3 MPIE Description 0 Multiprocessor interrupts are disabled normal receive operation initial value ...

Page 516: ...mode or when an external clock source is selected CKE1 1 Select the SCI operating mode in the serial mode register SMR before setting CKE1 and CKE0 For further details on selection of the SCI clock source see table 14 9 in section 14 3 Operation Bit 1 CKE1 Bit 0 CKE0 Description 1 0 0 Asynchronous mode Internal clock SCK pin used for input pin input signal is ignored or output pin output level is ...

Page 517: ... ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 R W R W R W R W R W R W R R R W Note The only value that can be written is a 0 to clear the flag Bit 7 Transmit Data Register Empty TDRE Indicates that the SCI has loaded transmit data from the TDR into the TSR and new serial transmit data can be written in the TDR Bit 7 TDRE Description 0 TDR contains valid transmit data TDRE is cleared to...

Page 518: ... reception of the next data ends an overrun error ORER occurs and the received data is lost Bit 5 Overrun Error ORER Indicates that data reception ended abnormally due to an overrun error Bit 5 ORER Description 0 Receiving is in progress or has ended normally initial value Clearing the RE bit to 0 in the serial control register does not affect the ORER bit which retains its previous value ORER is ...

Page 519: ...mitting is also disabled FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0 Bit 3 Parity Error PER Indicates that data reception with parity ended abnormally due to a parity error in the asynchronous mode Bit 3 PER Description 0 Receiving is in progress or has ended normally initial value Clearing the RE bit to 0 in the serial control register does not affect t...

Page 520: ...e value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in the asynchronous mode The MPB is a read only bit and cannot be written Bit 1 MPB Description 0 Multiprocessor bit value in receive data is 0 initial value If RE is cleared to 0 when a multiprocessor format is selected the MPB retains its previous value 1 Multiprocessor bit value in receive d...

Page 521: ... 1 1 R W R W R W R W R W R W R W R W R W Table 14 3 lists examples of BRR settings in the asynchronous mode table 14 4 lists examples of BBR settings in the clock synchronous mode Table 14 3 Bit Rates and BRR Settings in Asynchronous Mode φ MHz Bit Rate 4 4 9152 6 Bits s n N Error n N Error n N Error 110 2 70 0 03 2 86 0 31 2 106 0 44 150 1 207 0 16 1 255 0 00 2 77 0 16 300 1 103 0 16 1 127 0 00 1...

Page 522: ...2 127 0 00 300 1 191 0 00 1 207 0 16 1 255 0 00 600 1 95 0 00 1 103 0 16 1 127 0 00 1200 0 191 0 00 0 207 0 16 0 255 0 00 2400 0 95 0 00 0 103 0 16 0 127 0 00 4800 0 47 0 00 0 51 0 16 0 63 0 00 9600 0 23 0 00 0 25 0 16 0 31 0 00 14400 0 15 0 00 0 16 2 12 0 20 1 59 19200 0 11 0 00 0 12 0 16 0 15 0 00 28800 0 7 0 00 0 8 3 55 0 10 3 03 31250 0 6 5 33 0 7 0 00 0 9 1 70 38400 0 5 0 00 0 6 6 99 0 7 0 00...

Page 523: ... 155 0 16 300 2 64 0 16 2 71 0 00 2 77 0 16 600 1 129 0 16 1 143 0 00 1 155 0 16 1200 1 64 0 16 1 71 0 00 1 77 0 16 2400 0 129 0 16 0 143 0 00 0 155 0 16 4800 0 64 0 16 0 71 0 00 0 77 0 16 9600 0 32 1 36 0 35 0 00 0 38 0 16 14400 0 21 1 36 0 23 0 00 0 25 0 16 19200 0 15 1 73 0 17 0 00 0 19 2 34 28800 0 10 1 36 0 11 0 00 0 12 0 16 31250 0 9 0 00 0 10 0 54 0 11 0 00 38400 0 7 1 73 0 8 0 00 0 9 2 34 ...

Page 524: ... 191 0 00 300 2 79 0 00 2 90 0 16 2 95 0 00 600 1 159 0 00 1 181 0 16 1 191 0 00 1200 1 79 0 00 1 90 0 16 1 95 0 00 2400 0 159 0 00 0 181 0 16 0 191 0 00 4800 0 79 0 00 0 90 0 16 0 95 0 00 9600 0 39 0 00 0 45 0 93 0 47 0 00 14400 0 26 1 23 0 29 1 27 0 31 0 00 19200 0 19 0 00 0 22 0 93 0 23 0 00 28800 0 12 2 56 0 14 1 27 0 15 0 00 31250 0 11 2 40 0 13 0 00 0 14 1 70 38400 0 9 0 00 0 10 3 57 0 11 0 ...

Page 525: ...6 300 2 103 0 16 2 111 0 00 2 116 0 16 600 1 207 0 16 1 223 0 00 1 233 0 16 1200 1 103 0 16 1 111 0 00 1 116 0 16 2400 0 207 0 16 0 223 0 00 0 233 0 16 4800 0 103 0 16 0 111 0 00 0 116 0 16 9600 0 51 0 16 0 55 0 00 0 58 0 69 14400 0 34 0 79 0 36 0 90 0 38 0 16 19200 0 25 0 16 0 27 0 00 0 28 1 02 28800 0 16 2 12 0 18 1 75 0 19 2 34 31250 0 15 0 00 0 16 1 20 0 17 0 00 38400 0 12 0 16 0 13 0 00 0 14 ...

Page 526: ...0 16 300 2 119 0 00 2 127 0 00 2 129 0 16 600 1 239 0 00 1 255 0 00 2 64 0 16 1200 1 119 0 00 1 127 0 00 1 129 0 16 2400 0 239 0 00 0 255 0 00 1 64 0 16 4800 0 119 0 00 0 127 0 00 0 129 0 16 9600 0 59 0 00 0 63 0 00 0 64 0 16 14400 0 39 0 00 0 42 0 78 0 42 0 94 19200 0 29 0 00 0 31 0 00 0 32 1 36 28800 0 19 0 00 0 20 1 59 0 21 1 36 31250 0 17 2 40 0 19 1 70 0 19 0 00 38400 0 14 0 00 0 15 0 00 0 15...

Page 527: ... 16 300 2 142 0 16 2 143 0 00 2 155 0 16 600 2 71 0 54 2 71 0 00 2 77 0 16 1200 1 142 0 16 1 143 0 00 1 155 0 16 2400 1 71 0 54 1 71 0 00 1 77 0 16 4800 0 142 0 16 0 143 0 00 0 155 0 16 9600 0 71 0 54 0 71 0 00 0 77 0 16 14400 0 47 0 54 0 47 0 00 0 51 0 16 19200 0 35 0 54 0 35 0 00 0 38 0 16 28800 0 23 0 54 0 23 0 00 0 25 0 16 31250 0 21 0 00 0 21 0 54 0 23 0 00 38400 0 17 0 54 0 17 0 00 0 19 2 34...

Page 528: ...4 0 43 300 2 159 0 00 2 167 0 00 2 168 0 16 600 2 79 0 00 2 83 0 00 2 84 0 43 1200 1 159 0 00 1 167 0 00 1 168 0 16 2400 1 79 0 00 1 83 0 00 1 84 0 43 4800 0 159 0 00 0 167 0 00 0 168 0 16 9600 0 79 0 00 0 83 0 00 0 84 0 43 14400 0 52 0 63 0 55 0 00 0 55 0 76 19200 0 39 0 00 0 41 0 00 0 41 0 76 28800 0 26 1 23 0 27 0 00 0 27 0 76 31250 0 24 1 70 0 25 0 75 0 25 0 00 38400 0 19 0 00 0 20 0 00 0 20 0...

Page 529: ...95 0 00 300 2 175 0 00 2 181 0 16 2 191 0 00 600 1 87 0 00 2 90 0 16 2 95 0 00 1200 1 175 0 00 1 181 0 16 1 191 0 00 2400 1 87 0 00 1 90 0 16 1 95 0 00 4800 0 175 0 00 0 181 0 16 0 191 0 00 9600 0 87 0 00 0 90 0 16 0 95 0 00 14400 0 58 0 56 0 60 0 39 0 63 0 00 19200 0 43 0 00 0 45 0 93 0 47 0 00 28800 0 28 1 15 0 29 1 27 0 31 0 00 31250 0 26 0 12 0 27 0 00 0 28 1 69 38400 0 21 0 00 0 22 0 93 0 23 ...

Page 530: ...16 300 2 194 0 16 2 207 0 00 2 207 0 16 600 2 97 0 35 2 103 0 00 2 103 0 16 1200 1 194 0 16 1 207 0 00 1 207 0 16 2400 1 97 0 35 1 103 0 00 1 103 0 16 4800 0 194 0 16 0 207 0 00 0 207 0 16 9600 0 97 0 35 0 103 0 00 0 103 0 16 14400 0 64 0 16 0 68 0 48 0 68 0 64 19200 0 48 0 35 0 51 0 00 0 51 0 16 28800 0 32 1 36 0 34 0 95 0 34 0 79 31250 0 29 0 00 0 31 0 16 0 31 0 00 38400 0 23 1 73 0 25 0 00 0 25...

Page 531: ...0 45 300 2 214 0 07 2 215 0 00 2 216 0 01 600 2 106 0 39 2 107 0 00 2 108 0 45 1200 1 214 0 07 1 215 0 00 1 216 0 01 2400 1 106 0 39 1 107 0 00 1 108 0 45 4800 0 214 0 07 0 215 0 00 0 216 0 01 9600 0 106 0 39 0 107 0 00 0 108 0 45 14400 0 71 0 54 0 91 0 00 0 91 0 47 19200 0 53 0 54 0 53 0 00 0 53 0 47 28800 0 35 0 54 0 35 0 00 0 35 0 47 31250 0 32 0 00 0 32 0 54 0 32 1 01 38400 0 26 0 54 0 26 0 00...

Page 532: ...N 110 3 141 250 2 249 3 124 3 155 3 187 500 2 124 2 249 3 77 3 93 1k 1 249 2 124 2 155 2 187 2 5k 1 99 1 199 1 249 2 74 5k 0 199 1 99 1 124 1 149 10k 0 99 0 199 0 249 1 74 25k 0 39 0 79 0 99 0 119 50k 0 19 0 39 0 49 0 59 100k 0 9 0 19 0 24 0 29 250k 0 3 0 7 0 9 0 11 500k 0 1 0 3 0 4 0 5 1M 0 0 0 1 0 2 2 5M 0 0 0 0 5M ...

Page 533: ...110 250 3 249 500 3 124 3 155 3 187 3 218 1k 2 249 3 77 3 93 3 108 2 5k 2 99 2 124 2 149 2 174 5k 1 199 1 249 2 74 2 87 10k 1 99 1 124 1 149 1 174 25k 0 159 0 199 0 239 1 69 50k 0 79 0 99 0 119 0 139 100k 0 39 0 49 0 59 0 69 250k 0 15 0 19 0 23 0 27 500k 0 7 0 9 0 11 0 13 1M 0 3 0 4 0 5 0 6 2 5M 0 1 0 2 3 5M 0 1 5M 0 0 7M 0 0 ...

Page 534: ...25k 1 74 1 79 1 82 1 82 50k 0 149 0 159 0 164 0 166 100k 0 74 0 79 0 82 0 82 250k 0 29 0 31 0 32 0 32 500k 0 14 0 15 0 16 0 16 1M 0 7 0 7 0 7 0 7 2 5M 0 2 0 2 0 2 5M 7M Note Settings with an error of 1 or less are recommended Legend Blank No setting available Setting possible but error occurs Continuous transmission reception is not possible The BRR setting is calculated as follows Asynchronous mo...

Page 535: ...e of n SMR Settings n Clock Source CKS1 CKS2 0 φ 0 0 1 φ 4 0 1 2 φ 16 1 0 3 φ 64 1 1 The bit rate error in asynchronous mode is calculated as follows Error N 1 B 64 2 2n 1 100 1 6 φ 10 Table 14 5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used for various frequencies Tables 14 6 and 14 7 show the maximum rates for external clock input ...

Page 536: ...2500 0 0 11 0592 345600 0 0 12 375000 0 0 12 288 384000 0 0 14 437500 0 0 14 7456 460800 0 0 16 500000 0 0 17 2032 537600 0 0 18 562500 0 0 18 432 576000 0 0 19 6608 614400 0 0 20 625000 0 0 22 687500 0 0 22 1184 691200 0 0 24 750000 0 0 24 576 768000 0 0 25 8048 806400 0 0 26 812500 0 0 27 0336 844800 0 0 28 875000 0 0 29 4912 921600 0 0 30 937500 0 0 31 9488 998400 0 0 32 1000000 0 0 33 1031250 ...

Page 537: ... 0000 187500 12 288 3 0720 192000 14 3 5000 218750 14 7456 3 6864 230400 16 4 0000 250000 17 2032 4 3008 268800 18 4 5000 281250 18 432 4 6080 288000 19 6608 4 9152 307200 20 5 0000 312500 22 5 5000 343750 22 1184 5 5296 345600 24 6 0000 375000 24 576 6 1440 384000 25 8048 6 4512 403200 26 6 5000 406250 27 0336 6 7584 422400 28 7 0000 437500 29 4912 7 3728 460800 30 7 5000 468750 31 9488 7 9872 49...

Page 538: ...te Bits s 4 0 6667 666666 7 6 1 0000 1000000 0 8 1 3333 1333333 3 10 1 6667 1666666 7 12 2 0000 2000000 0 14 2 3333 2333333 3 16 2 6667 2666666 7 18 3 0000 3000000 0 20 3 3333 3333333 3 22 3 6667 3666666 7 24 4 0000 4000000 0 26 4 3333 4333333 3 28 4 6667 4666666 7 30 5 0000 5000000 0 32 5 3333 5333333 3 33 3333 5 5556 5555550 0 ...

Page 539: ...ing it is possible to detect framing errors FER parity errors PER overrun errors ORER and the break state An internal or external clock can be selected as the SCI clock source When an internal clock is selected the SCI operates using the on chip baud rate generator clock and can output a clock with a frequency matching the bit rate When an external clock is selected the external clock input must h...

Page 540: ...it 1 bit 1 2 bits Clock synchronous 1 8 bit Not set None Note Asterisks in the table indicate don t care bits Table 14 9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Settings SCI Transmit Receive Clock Mode Bit 7 C A Bit 1 CKE1 Bit 0 CKE0 Clock Source SCK Pin Function Asynchronous 0 0 0 Internal SCI does not use the SCK pin 1 Outputs a clock with frequency matching the bit rate 1 0 ...

Page 541: ...ly held in the marking high state The SCI monitors the line and starts serial communication when the line goes to the space low state indicating a start bit One serial character consists of a start bit low data LSB first parity bit high or low and stop bit high in that order When receiving in the asynchronous mode the SCI synchronizes on the falling edge of the start bit The SCI samples each data ...

Page 542: ...OP STOP 1 0 0 0 START 7 Bit data STOP 1 0 0 1 START 7 Bit data STOP STOP 1 1 0 0 START 7 Bit data P STOP 1 1 0 1 START 7 Bit data P STOP STOP 0 1 0 START 8 Bit data MPB STOP 0 1 1 START 8 Bit data MPB STOP STOP 1 1 0 START 7 Bit data MPB STOP 1 1 1 START 7 Bit data MPB STOP STOP Don t care bits Note START Start bit STOP Stop bit P Parity bit MPB Multiprocessor bit Clock An internal clock generated...

Page 543: ...ize the RDRF PER FER and ORER flags and receive data register RDR which retain their previous contents When an external clock is used the clock should not be stopped during initialization or subsequent operation SCI operation becomes unreliable if the clock is stopped Figure 14 4 is a sample flowchart for initializing the SCI The procedure is as follows the steps correspond to the numbers in the f...

Page 544: ...zation Set the TxD pin using the PFC 2 SCI status check and transmit data write Read the serial status register SSR check that the TDRE bit is 1 then write transmit data in the transmit data register TDR and clear TDRE to 0 3 Continue transmitting serial data Read the TDRE bit to check whether it is safe to write if it reads 1 if so write data in TDR then clear TDRE to 0 When the DMAC or the DTC i...

Page 545: ...SCR to 0 select theTxD pin as an output port with the PFC TEND 1 End transmission 1 2 3 No Yes TDRE 1 Write transmission data to TDR and clear TDRE bit in SSR to 0 All data transmitted No Yes Output break signal No Yes Set DR 0 4 Yes No Figure 14 5 Sample Flowchart for Transmitting Serial Data ...

Page 546: ...ts of data are output LSB first c Parity bit or multiprocessor bit one parity bit even or odd parity or one multiprocessor bit is output Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit one or two 1 bits stop bits are output e Marking output of 1 bits continues until the start bit of the next transmit data 3 The SCI checks the TDRE bit when i...

Page 547: ...etection If a receive error occurs read the ORER PER and FER bits of the SSR to identify the error After executing the necessary error handling clear ORER PER and FER all to 0 Receiving cannot resume if ORER PER or FER remain set to 1 When a framing error occurs the RxD pin can be read to detect the break state 3 SCI status check and receive data read Read the serial status register SSR check that...

Page 548: ...R Read reception data of RDR and clear RDRF bit in SSR to 0 End reception 1 4 No No Yes Yes Read the RDRF bit in SSR RDRF 1 PER FER ORER 1 Clear the RE bit of SCR to 0 Yes No 3 Error handling 2 All data received Figure 14 7 Sample Flowchart for Receiving Serial Data 1 ...

Page 549: ... Overrun error handling FER 1 Yes Break No Framing error handling PER 1 Yes Parity error handling Clear ORER PER and FER to 0 in SSR End Clear RE bit in SCR to 0 No No No Yes Yes Figure 14 8 Sample Flowchart for Receiving Serial Data 2 ...

Page 550: ...operates as indicated in table 14 11 Note When a receive error occurs further receiving is disabled While receiving the RDRF bit is not set to 1 so be sure to clear the error flags 4 After setting RDRF to 1 if the receive data full interrupt enable bit RIE is set to 1 in the SCR the SCI requests a receive data full interrupt RxI If one of the error flags ORER PER or FER is set to 1 and the receive...

Page 551: ... sending cycle that identifies the receiving processor and a data sending cycle The multiprocessor bit distinguishes ID sending cycles from data sending cycles The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1 Next the transmitting processor sends transmit data with the multiprocessor bit c...

Page 552: ...ws a sample flowchart for transmitting multiprocessor serial data The procedure is as follows the steps correspond to the numbers in the flowchart 1 SCI initialization Set the TxD pin using the PFC 2 SCI status check and transmit data write Read the serial status register SSR check that the TDRE bit is 1 then write transmit data in the transmit data register TDR Also set MPBT multiprocessor bit tr...

Page 553: ...R Output break signal Yes Set DR 0 Clear TE bit in SCR to 0 select theTxD pin function as an output port with the PFC End transmission Yes Read TDRE bit in SSR Clear TDRE bit to 0 Initialization No No Yes No No 1 2 3 4 Start transmission Figure 14 11 Sample Flowchart for Transmitting Multiprocessor Serial Data ...

Page 554: ... bit one 0 bit is output b Transmit data seven or eight bits are output LSB first c Multiprocessor bit one multiprocessor bit MPBT value is output d Stop bit one or two 1 bits stop bits are output e Marking output of 1 bits continues until the start bit of the next transmit data 3 The SCI checks the TDRE bit when it outputs the stop bit If TDRE is 0 the SCI loads data from the TDR into the TSR out...

Page 555: ...ceive cycle Set the MPIE bit in the serial control register SCR to 1 3 SCI status check and compare to ID reception Read the serial status register SSR check that RDRF is set to 1 then read data from the receive data register RDR and compare with the processor s own ID If the ID does not match the receive data set MPIE to 1 again and clear RDRF to 0 If the ID matches the receive data clear RDRF to...

Page 556: ...RE bit in SCR to 0 Yes No 1 2 3 Read ORER and FER bits of SSR FER 1 or ORER 1 Read RDRF bit in SSR Read receive data from RDR Is ID the station s ID No Read ORER and FER bits in SSR Read receive data from RDR No Error processing No Yes 5 4 Yes Yes No Yes Start reception Figure 14 13 Sample Flowchart for Receiving Multiprocessor Serial Data ...

Page 557: ...ing error handling Yes Start error handling Overrun error handling Yes FER 1 Clear ORER and FER bits in SSR to 0 End No No No Clear RE bit in SCR to 0 Figure 14 13 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...

Page 558: ...rocessor interrupt MPIE 0 RxI interrupt handler reads data in RDR and clears RDRF to 0 Not station s ID so MPIE is set to 1 again No RxI interrupt RDR maintains state 0 1 1 1 1 0 1 Serial data Start bit Stop bit Start bit Stop bit Idling marking D0 D1 D7 D0 D1 D7 0 MPB MPB MPB Data ID1 Data data 1 Figure 14 14 SCI Receive Operation ID Does Not Match ...

Page 559: ...ocessor bit and one stop bit Figure 14 15 Example of SCI Receive Operation ID Matches 14 3 4 Clock Synchronous Operation In the clock synchronous mode the SCI transmits and receives data in synchronization with clock pulses This mode is suitable for high speed serial communication The SCI transmitter and receiver are independent so full duplex communication is possible while sharing the same clock...

Page 560: ... pin can be selected as the SCI transmit receive clock The clock source is selected by the C A bit in the serial mode register SMR and bits CKE1 and CKE0 in the serial control register SCR See table 14 9 When the SCI operates on an internal clock it outputs the clock signal at the SCK pin Eight clock pulses are output per transmitted or received character When the SCI is not transmitting or receiv...

Page 561: ... interval required to transmit or receive one bit then set TE or RE in the serial control register SCR to 1 Also set RIE TIE TEIE and MPIE The TxD RxD pins becomes usable in response to the PFC corresponding bits and the TE RE bit settings Start of initialization Clear TE and RE bits to 0 in SCR 1 bit interval elapsed Set TE and RE to 1 in SCR Set RIE TIE TEIE and MPIE bits Yes No 1 Set RIE TIE TE...

Page 562: ...transmit data write Read SSR check that the TDRE flag is 1 then write transmit data in TDR and clear the TDRE flag to 0 3 To continue transmitting serial data After checking that the TDRE flag is 1 indicating that data can be written write data in TDR then clear the TDRE flag to 0 When the DMAC or DTC is activated by a transmit data empty interrupt request TxI to write data in TDR the TDRE flag is...

Page 563: ... SSR TDRE 1 Write transmit data in TDR and clear TDRE flag to 0 in SSR All data transmitted Read TEND flag in SSR Yes No No No Yes TEND 1 Yes End Clear TE bit to 0 in SCR Initialize 2 3 1 Figure 14 18 Sample Flowchart for Serial Transmitting ...

Page 564: ... the transmit data empty interrupt enable bit TIE in the SCR is set to 1 the SCI requests a transmit data empty interrupt TxI at this time If clock output mode is selected the SCI outputs eight synchronous clock pulses If an external clock source is selected the SCI outputs data in synchronization with the input clock Data are output from the TxD pin in order from the LSB bit 0 to the MSB bit 7 3 ...

Page 565: ... read the ORER bit in SSR to identify the error After executing the necessary error handling clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 3 SCI status check and receive data read Read the serial status register SSR check that RDRF is set to 1 then read receive data from the receive data register RDR and clear RDRF to 0 The RxI interrupt can also be used to determin...

Page 566: ...of SSR All data received End reception 1 No Yes ORER 1 Read receive data from RDR and clear RDRF bit of SSR to 0 RDRF 1 Yes Yes No Clear RE bit of SCR to 0 No Read RDRF bit of SSR Error processing 3 4 2 Figure 14 20 Sample Flowchart for Serial Receiving 1 ...

Page 567: ... ORER Figure 14 22 Example of SCI Receive Operation In receiving the SCI operates as follows 1 The SCI synchronizes with serial clock input or output and initializes internally 2 Receive data is shifted into the RSR in order from the LSB to the MSB After receiving the data the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the RDR If this check passes the SCI sets R...

Page 568: ...eive error occurs read the ORER bit in SSR to identify the error After executing the necessary error processing clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 4 SCI status check and receive data read Read the serial status register SSR check that RDRF is set to 1 then read receive data from the receive data register RDR and clear RDRF to 0 The RxI interrupt can also ...

Page 569: ...tion 1 2 No Yes TDRE 1 Write transmission data in TDR and clear TDRE bit of SSR to 0 RDRF 1 Yes No Clear TE and RE bits of SCR to 0 Yes No Read ORER bit of SSR Error handling 3 ORER 1 Yes Read receive data of RDR and clear RDRF bit of SSR to 0 Read RDRF bit of SSR 4 5 No Figure 14 23 Sample Flowchart for Serial Transmission ...

Page 570: ...C or the DTC writes data in the transmit data register TDR RxI is requested when the RDRF bit in the SSR is set to 1 RxI can start the DMAC or the DTC to transfer data RDRF is automatically cleared to 0 when the DMAC or the DTC reads the receive data register RDR ERI is requested when the ORER PER or FER bit in the SSR is set to 1 ERI cannot start the DMAC or the DTC TEI is requested when the TEND...

Page 571: ...to check that TDRE is set to 1 14 5 2 Simultaneous Multiple Receive Errors Table 14 13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously When an overrun error occurs the RSR contents cannot be transferred to the RDR so receive data is lost Table 14 13 SSR Status Flags and Transfer of Receive Data SSR Status Flags Receive Data Transfer Receive Error Statu...

Page 572: ...put a 1 To send a break in serial transmission first clear the DR to 0 then establish the TxD pin as an output port using the PFC When TE is cleared to 0 the transmission section is initialized regardless of the present transmission status 14 5 5 Receive Error Flags and Transmitter Operation Clock Synchronous Mode Only When a receive error flag ORER PER or FER is set to 1 the SCI will not start tr...

Page 573: ...receive margin in the asynchronous mode can therefore be expressed as M 0 5 1 2N L 0 5 F D 0 5 N 1 F 100 M Receive margin N Ratio of clock frequency to bit rate N 16 D Clock duty cycle D 0 1 0 L Frame length L 9 12 F Absolute deviation of clock frequency From the equation above if F 0 and D 0 5 the receive margin is 46 875 D 0 5 F 0 M 0 5 1 2 16 100 46 875 This is a theoretical value A reasonable ...

Page 574: ...K TDRE t Note During external clock operation an error may occur if t is 4φ or less Figure 14 25 Example of Clock Synchronous Transmission with DMAC 14 5 8 Cautions for Clock Synchronous External Clock Mode Set TE RE 1 only when the external clock SCK is 1 Do not set TE RE 1 until at least four clocks after the external clock SCK has changed from 0 to 1 When receiving RDRF is 1 when RE is set to z...

Page 575: ... Vref only with SH7043 High speed conversion Minimum conversion time 2 9 µs per channel for 28 MHz operation 1 4 µs per channel during continuous conversion Multiple conversion modes Select mode group mode Single mode scan mode Buffered operation possible 2 channel simultaneous sampling possible Three types of conversion start Software timer conversion start trigger MTU or ADTRG pin can be selecte...

Page 576: ...DDRB ADDRC ADDRD A D control register A D control status register A D data register A A D data register B A D data register C A D data register D CMP S H ADDRE ADDRF ADDRG ADDRH Comparator array Sample and hold circuit A D data register E A D data register F A D data register G A D data register H Note SH7043 only Figure 15 1 High Speed A D Converter Block Diagram 15 1 3 Pin Configuration Table 15...

Page 577: ...annel 7 A D external trigger input ADTRG I External trigger for A D conversion start 15 1 4 Register Configuration Table 15 2 shows the configuration of the high speed A D converter registers Table 15 2 Register Configuration Name Abbreviation R W Initial Value Address Access Size A D data register A ADDRA R H 0000 H FFFF83F0 8 16 A D data register B ADDRB R H 0000 H FFFF83F2 A D data register C A...

Page 578: ...pper 2 bits are stored into the upper byte bits 9 8 Bits 15 10 always read as 0 Data reads can be either byte or word The upper 8 bits of the converted data are transferred upon byte data reads Additionally buffered operation is possible by combining ADDRA ADDRD Table 15 3 shows the correspondence between the analog input channels and the ADDR The ADDR are initialized to H 0000 by power on reset o...

Page 579: ...ontrol Status Register ADCSR The ADCSR is an 8 bit read write register used for A D conversion operation control and to indicate status The ADCSR is initialized to H 00 by power on reset or in standby mode Manual reset does not initialize ADCSR Bit 7 6 5 4 3 2 1 0 ADF ADIE ADST CKS GRP CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note The only value that can be wri...

Page 580: ... Enables or disables interrupt requests ADI after A D conversion ends Set the ADIE bit while conversion is suspended Bit 6 ADIE Description 0 Disables interrupt requests ADI after A D conversion ends initial value 1 Enables interrupt requests ADI after A D conversion ends Bit 5 A D Start ADST Selects start or stop for A D conversion A 1 is maintained during A D conversions The ADST bit can be set ...

Page 581: ...p Mode GRP Designates either select mode or group mode for the A D conversion channel selection Set the GRP bit only while conversion is halted Bit 3 GRP Description 0 Select mode initial value 1 Group mode Bits 2 0 Channel Select 2 0 CH2 CH0 These bits along with the GRP bit select the analog input channel Set the input channel only while conversion is halted Description Bit 2 CH2 Bit 1 CH1 Bit 0...

Page 582: ...conversion start operation Set the PWR bit only while conversion is halted Bit 6 PWR Description 0 Low power conversion mode initial value 1 High speed start mode Bits 5 and 4 Timer Trigger Select 1 0 TRGS1 TRGS0 These bits enable or prohibit A D conversion starts by trigger signals Set the TRGS1 TRGS0 bits only while conversion is halted Bit 5 TRGS1 Bit 4 TRGS0 Description 0 0 Enable A D conversi...

Page 583: ...onversion result ADDRA ADDRB ADDRB is the buffer register 1 0 ADDRA and ADDRC also ADDRB and ADDRD buffer operation conversion result 1 ADDRA ADDRC conversion result 2 ADDRB ADDRD ADDRC and ADDRD are buffer registers 1 1 ADDRA ADDRD buffer operation conversion result ADDRA ADDRB ADDRC ADDRD ADDRB ADDRD are buffer registers 15 3 Bus Master Interface The ADDRA ADDRH are 16 bit registers with a 16 bi...

Page 584: ...546 0 0 0 0 0 0 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 Upper 8 bits Internal data bus Bus I F Data register Word data read Lower 8 bits Figure 15 2 ADDR Read Operation 1 ...

Page 585: ...547 0 0 0 0 0 0 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 Upper 8 bits Internal data bus Bus I F Byte data read Data register Figure 15 3 ADDR Read Operation 2 ...

Page 586: ... mode or low power conversion mode can be selected for A D conversion using the PWR bit setting When changing the operation mode or input channel rewrite the ADCSR ADCR while the ADST bit is cleared to 0 After rewriting the ADCSR ADCR A D conversion will be restarted when the ADST bit is set to 1 Operation mode or input channel changes can be made simultaneously with ADST bit setting When stopping...

Page 587: ...ne channel When the ADST bit is set to 1 A D conversion is started according to the designated conversion start conditions The ADST bit is held to 1 until 0 cleared by software A D conversion for the selected input channel is repeated during that interval The ADF flag is set to 1 at the end of the first conversion At this point if the ADIE bit is set an ADI interrupt request is issued and the A D ...

Page 588: ...Example Select Scan Mode 15 4 3 Group Single Mode Choose group single mode when doing A D conversions for multiple channels When the ADST bit is set to 1 A D conversion is started according to the designated conversion start conditions The ADST bit is held to 1 during A D conversion and is automatically cleared to 0 when all conversions for the designated input channels are completed The ADF flag ...

Page 589: ...nels This is useful when doing continuous monitoring of the analog inputs of multiple channels When the ADST bit is set to 1 A D conversion is started according to the designated conversion start conditions The ADST bit is held to 1 until 0 cleared by software A D conversion for the selected input channels is repeated during that interval The ADF flag is set to 1 at the completion of the first con...

Page 590: ...er sion standby Cleared to 0 by software Set to 1 by software Conversion result 1 Conversion result 4 Conversion result 5 Conversion result 2 Conversion result 3 Conver sion stopped Figure 15 7 A D Converter Operation Example Group Scan Mode 15 4 5 Buffer Operation When conversion ends on the relevant channel the conversion result is stored in the ADDR and simultaneously the previously stored resu...

Page 591: ...sult 4 Conver sion result 1 Conver sion result 2 Conver sion result 3 Figure 15 8 Buffer Operation Example Select Scan Mode Two Stage One Group Operation When CH2 CH0 B 001 Buffer Only Operation When performing conversion only on the analog input channels specified by the BUFE1 and BUFE0 bits select group mode and you can select the ADF flag setting conditions with the CH2 CH0 bits Table 15 4 show...

Page 592: ...ADDRB AN0 2 times ADDRB 1 0 AN0 AN1 2 times ADDRD AN0 3 times ADDRC 1 AN0 4 times ADDRD 1 Note See table 15 5 Combined Group Mode and Buffer Operation Continuous conversion is possible on analog input channels AN0 and AN1 specified by bits BUFE1 and BUFE0 as well as AN4 AN7 due to setting of bits CH2 CH0 Table 15 5 shows conversion during buffer operation and ADF flag setting conditions The ADF fl...

Page 593: ...rations Clear the BUFE1 and BUFE0 bits to B 00 in conversion standby mode or when the converter has been halted The number of buffer operations is cleared to 0 Updating Buffer Operations Clear the BUFE1 and BUFE0 bits to B 00 in conversion standby mode or when the converter has been halted Thereafter set BUFE1 and BUFE0 and the buffer operations shown in tables 15 4 and 15 5 are performed when con...

Page 594: ...ADST ADF ADDRD ADDRC Automatically cleared Channel 0 Channel 1 Channel 2 Channel 3 Sampling 1 A D conver sion 1 A D conver sion 2 conver sion standby Conversion standby Conversion standby Conversion standby Conver sion standby Sampling 2 Conver sion standby Conver sion standby Set to 1 by software Conversion result 1 Conversion result 2 Figure 15 9 Simultaneous Sampling Operation Group Single Mode...

Page 595: ...d in 10 cycles Select the basic clock with the CKS bit of the ADCSR When the A D conversion ends ADST is cleared to 0 and the analog circuit power supply is automatically cut off Because the analog circuit is only active during the A D conversion operation period in this mode current consumption can be reduced In high speed start mode ADST is cleared to 0 when A D conversion ends Power continues t...

Page 596: ...re Analog circuit power supply 200 cycles Set Clear Sam pling 1 Sam pling 2 Sam pling 3 A D conver sion 1 A D conver sion 2 A D conver sion 3 Conver sion standby Conver sion standby Conver sion standby Conver sion standby Cleared to 0 by software Conversion result 1 Conversion result 2 Conversion result 3 Figure 15 10 Conversion Start Operation Low Power Conversion Mode ...

Page 597: ...el 2 Channel 3 Set to 1 by software Sam pling 1 Sam pling 2 A D conver sion 1 A D conver sion 2 Conversion result 1 Conversion result 2 Conversion standby Conversion standby Conversion standby Conversion standby 200 cycles Switched on by software PWR set to 1 PWR cleared to 0 Figure 15 11 Conversion Start Operation High Speed Start Mode ...

Page 598: ...on is started The other operations are the same as when the ADST bit is set to 1 by software Figure 15 12 shows an example of the timing when the ADST bit is set by an external input ADDRB ADDRA ADST ADDRD ADDRC ADF Set ADTRG external trigger Channel 0 Channel 1 Channel 2 Channel 3 Sam pling 1 A D conver sion 1 Conver sion standby Conversion standby Conversion standby Conversion standby Conversion...

Page 599: ... the input sampling time tSPL and the operating time tCP This conversion time is not a set value but is decided by the tD ADCSR write timing or the timer conversion start trigger generation timing Figure 15 13 shows an example of A D conversion timing Table 15 7 lists A D conversion times Address Write signal ADST Sampling timing φ ADF tD tCONV tSPL tCP t D t SPL t CONV t CP A D conversion start d...

Page 600: ... operating frequency and CKS bit settings Table 15 8 Operating Frequency and CKS Bit Settings Conversion Time Minimum Conversion Time µs CKS States 28 MHz 20 MHz 16 MHz 10 MHz 8 MHz 0 42 5 2 1 2 6 4 3 5 3 1 82 5 2 9 4 2 5 0 8 3 10 3 Note The indication means the setting is not available 15 5 Interrupts The high speed A D converter generates an A D conversion end interrupt ADI upon completion of A ...

Page 601: ...sing the A D converter use AVref Vcc During the standby mode use VRAM AVref AVcc VRAM is the RAM standby voltage 4 Input ports The time constant for the circuit connecting to the input port must be shorter than the sampling time of the A D converter Input voltage may not be sampled sufficiently when the time constant of the circuit is long 5 Conversion start modes Depending on the PWR bit setting ...

Page 602: ...AN0 to AN7 This LSI 10µF 0 01µF 100Ω Rin 2 0 1µF 1 1 Figure 15 14 Example of a Protection Circuit for the Analog Input Pins AN0 to AN7 1 0kΩ 20pF 1MΩ High speed A D converter Analog multiplexer Note Numbers are only to be noted as reference value Figure 15 15 Equivalent Circuit of Analog Input Pins ...

Page 603: ...565 Table 15 10 Analog Input Pin Specification Item Min Max Unit Analog input capacity 20 pF Permitted source impedance 1 kΩ ...

Page 604: ...566 ...

Page 605: ... and SH7045 Connected to AVCC internally in the SH7040A SH7042A and SH7044 High speed conversion Minimum conversion time per channel Operation frequency f 20MHz CKS 0 1 6 7µs 20MHz CKS 1 Operation frequency f 20MHz CKS 0 9 3µs 28 7MHz CKS 0 Multiple conversion modes Single mode scan mode 2 channel simultaneous conversion Three types of conversion start Software timer conversion start trigger MTU o...

Page 606: ...le data bus Module data bus Only with 144 pin Only with 144 pin 10 bit D A Continuous comparison register ADDRA0 ADDRB0 ADDRC0 ADDRD0 ADCSR0 ADCR0 Bus interface Analog multiplexer Continuous comparison register ADDRA1 ADDRB1 ADDRC1 ADDRD1 ADCSR1 ADCR1 Bus interface 10 bit D A Analog multiplexer Sample hold circuit Comparator Control circuit Sample hold circuit Comparator Control circuit Port trigg...

Page 607: ...ndard voltage Standard voltage AVref I A D conversion standard voltage SH7041A SH7043A and SH7045 only A D0 Analog input 0 AND I Analog input channel 0 Analog input 1 AN1 I Analog input channel 1 Analog input 2 AN2 I Analog input channel 2 Analog input 3 AN3 I Analog input channel 3 A D1 Analog input 4 AN4 I Analog input channel 4 Analog input 5 AN5 I Analog input channel 5 Analog input 6 AN6 I An...

Page 608: ...FFF8406 8 16 A D0 data register DL ADDRD0L R H 00 H FFFF8407 8 A D0 control status register ADCSR0 R W H 00 H FFFF8410 8 16 A D0 control register ADCR0 R W H 7F H FFFF8412 8 16 A D1 data register AH ADDRA1H R H 00 H FFFF8408 8 16 A D1 data register AL ADDRA1L R H 00 H FFFF8409 8 A D1 data register BH ADDRB1H R H 00 H FFFF840A 8 16 A D1 data register BL ADDRB1L R H 00 H FFFF840B 8 A D1 data registe...

Page 609: ...Analog input channels and correspondence to ADDR are shown in table 16 3 ADDR can always be read from the CPU The upper byte may be read directly The lower byte is transferred through the temporary register TEMP For details see section 16 3 Interface with CPU ADDR is initialized to H 0000 during power on reset or standby mode ADDR will not be initialized by manual reset 15 14 13 12 11 10 9 8 7 6 5...

Page 610: ...lag Bit 7 A D End Flag ADF Status flag that indicates end of A D conversion Bit 7 ADF Description 0 Clear conditions Initial value 1 Writing 0 to ADF after reading ADF with ADF 1 2 When registers of the mid speed converter are accessed after the DMAC and DTC are activated by ADI interrupt 1 Set conditions 1 Single mode When A D conversion is complete 2 Scan mode When A D conversion of all designat...

Page 611: ...Selects the A D conversion mode from single mode and scan mode For operations during single scan mode see section 16 4 Operation When switching modes proceed while ADST 0 Bit 4 SCAN Description 0 Single mode Initial value 1 Scan mode Bit 3 Clock Select CKS Sets the A D conversion time Proceed conversion time switch while adst 0 Always set CKS 0 when operating frequency exceeds 20MHz Bit 3 CKS Desc...

Page 612: ... to H 7F during power on reset and standby mode Manual reset does not initialize ADCR TRGE 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 R W R W R R R R R R R Initial value Bit Bit 7 Trigger Enable TRGE Enables or disables A D conversion start of input from external or MTU trigger Bit 7 TRGE Description 0 Disables A D conversion start of external or MTU trigger Initial value 1 Starts A D conversion on last tran...

Page 613: ...CPU and the lower byte data is transferred to TEMP of the mid speed A D converter Next read the lower byte to read the TEMP contents into the CPU When reading the ADDR in byte size read the upper byte before the lower byte Furthermore it is possible to read only the upper byte however please note that contents are not guaranteed when reading only the lower byte In addition when reading ADDR in wor...

Page 614: ...he ADST bit to 0 and stop A D conversion to avoid malfunction After switching mode channel change and ADST bit setting can be made at the same time set the ADST bit to 1 to restart A D conversion An example of operation when channel 1 AN1 is selected in the single mode is shown in figure 16 3 the bit specification in the example is the ADCSR0 register 1 Set operation mode to single mode SCAN 0 inp...

Page 615: ... Channel 1 AN1 Operation state Channel 2 AN2 Operation state Conversion standby Conversion standby Conversion standby Conversion standby Conversion standby Conversion standby A D conversion 1 A D conversion 2 Reading conversion result Reading conversion result A D conversion result 1 A D conversion result 2 Figure 16 3 Operation Example of Mid speed A D Converter Single Mode Channel 1 Selected ...

Page 616: ...operation when three channels of A D0 AN0 2 are selected for A D conversion is shown in figure 16 4 the bit specification in the example is the ADCSR0 register 1 Set operation mode to scan mode SCAN 1 set analog channels to AN0 2 CH1 1 CH0 0 then start A D conversion ADST 1 2 When A D conversion for channel 1 is complete A D conversion result is transferred to ADDRA0 Next channel 2 AN1 will automa...

Page 617: ...rsion standby Conversion standby Conversion standby Conversion standby Conversion standby A D conversion 1 A D conversion 2 A D conversion 3 A D conversion 4 A D conversion 5 A D conversion time Transfer A D conversion result 1 A D conversion result 4 A D conversion result 2 A D conversion result 3 Notes 1 indicates command execution by the software 2 Data is ignored during conversion Figure 16 4 ...

Page 618: ... both tD and input sampling time Here tD is determined by the write timing to ADCSR and is not constant Thus the conversion time changes in the range shown in table 16 4 The conversion time shown in table 16 4 is the time for the first conversion For the second conversion and after the time will be 256 state fixed for CKS 0 and 128 state fixed for CKS 1 1 2 CK ADF t D t SPL t CONV Key 1 Write cycl...

Page 619: ...External trigger input is input from the ADTRG pin or MTU when the TRGE bit of the A D control register ADCR is set to 1 A D conversion is started when the ADST bit of the A D control status register ADCSR is set to 1 by the ADTRG input pin last transition edge or MTU trigger Other operations regardless of whether in the single or scan mode are the same as when setting the ADST bit to 1 with the s...

Page 620: ...s of the mid speed A D converter Table 16 5 Mid speed A D Converter Interrupt Factors Mid speed A D converter Interrupt Factor Content DTC DMAC A D0 ADI0 Interrupt by conversion complete O A D1 ADI1 O O activation enabled activation disabled When accessing the A D0 register with DTC activated by ADI0 interrupt the ADF bit of the A D0 control status register ADCSR0 will automatically be cleared to ...

Page 621: ... the figure to 0000000001 001 in the figure Full scale error see figure 16 7 2 is the deviation between the actual A D conversion characteristic and the ideal A D conversion characteristic when the digital output value changes from 1111111110 110 in the figure to the maximum value full scale voltage of 111111111 111 in the figure Quantization error is the deviation inherent in the medium speed A D...

Page 622: ...When the medium speed A D converter is not used set AVref AVCC 4 AVCC and AVref must be connected to the power supply VCC even if the medium speed A D converter is not used or is in standby mode 16 7 2 Handling of Analog Input Pins To prevent damage from surges and other abnormal voltages at the analog input pins AN0 AN7 connect a protection circuit such as that shown in figure 16 8 This circuit a...

Page 623: ...VCC AVref AN0 AN15 AVSS This LSI Notes Numbers are only to be noted as reference value 1 2 Rin Input impedance 10 µF 0 01 µF Rin 2 0 1 µF 100 Ω 1 1 Figure 16 8 Example of Analog Input Pin Protection Circuit ...

Page 624: ...speed A D converter Note Numbers are only to be noted as reference value Figure 16 9 Equivalent Circuit for the Analog Input Pins Table 16 6 Analog Pin Specifications Item Min Max Unit Analog input capacitance 20 pF Permissible signal source impedance 1 kΩ ...

Page 625: ... generate interrupts at set intervals 17 1 1 Features The CMT has the following features Four types of counter input clock can be selected One of four internal clocks φ 8 φ 32 φ 128 φ 512 can be selected independently for each channel Interrupt sources A compare match interrupt can be requested independently for each channel 17 1 2 Block Diagram Figure 17 1 shows a block diagram of the CMT ...

Page 626: ... 512 CMCSR1 CMCOR1 CMCNT1 CMCNT0 CMCOR0 Comparator CMSTR CMCSR0 Comparator Bus interface Module bus CMT CMSTR CMCSR CMCOR CMCNT CMI Compare match timer start register Compare match timer control status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 17 1 CMT Block Diagram ...

Page 627: ...r 0 CMCSR0 R W H 0000 H FFFF83D2 8 16 32 Compare match timer counter 0 CMCNT0 R W H 0000 H FFFF83D4 8 16 32 Compare match timer constant register 0 CMCOR0 R W H FFFF H FFFF83D6 8 16 32 1 Compare match timer control status register 1 CMCSR1 R W H 0000 H FFFF83D8 8 16 32 Compare match timer counter 1 CMCNT1 R W H 0000 H FFFF83DA 8 16 32 Compare match timer constant register 1 CMCOR1 R W H FFFF H FFF...

Page 628: ...ue 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 STR1 STR0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R W R W Bits 15 2 Reserved These bits always read as 0 The write value should always be 0 Bit 1 Count Start 1 STR1 Selects whether to operate or halt compare match timer counter 1 Bit 1 STR1 Description 0 CMCNT1 count operation halted initial value 1 CMCNT1 count operation Bit 0 Count...

Page 629: ... R W R R R R R W R W Note The only value that can be written is a 0 to clear the flag Bits 15 8 and 5 2 Reserved These bits always read as 0 The write value should always be 0 Bit 7 Compare Match Flag CMF This flag indicates whether or not the CMCNT and CMCOR values have matched Bit 7 CMF Description 0 CMCNT and CMCOR values have not matched initial status Clear condition Write a 0 to CMF after re...

Page 630: ... When an internal clock is selected with the CKS1 CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1 the CMCNT begins incrementing with that clock When the CMCNT value matches that of the compare match timer constant register CMCOR the CMCNT is cleared to H 0000 and the CMF flag of the CMCSR is set to 1 If the CMIE bit of the CMCSR is set to 1 at this time a compare match int...

Page 631: ...1 Period Count Operation When an internal clock is selected with the CKS1 CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1 the CMCNT begins incrementing with the selected clock When the CMCNT counter value matches that of the compare match constant register CMCOR the CMCNT counter is cleared to H 0000 and the CMF flag of the CMCSR register is set to 1 If the CMIE bit of the...

Page 632: ...request the priority between the channels can be changed by using the interrupt controller settings See section 6 Interrupt Controller INTC for details Interrupt requests can also be used as data transfer controller DTC activating sources In this case channel priorities are fixed See section 8 Data Transfer Controller DTC for details 17 4 2 Compare Match Flag Set Timing The CMF bit of the CMCSR re...

Page 633: ... Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1 or by a clear signal after a DTC transfer Figure 17 5 shows the timing when the CMF bit is cleared by the CPU T2 T1 CK CMF CMCSR write cycle Figure 17 5 Timing of CMF Clear by the CPU ...

Page 634: ...are Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle the CMCNT counter clear has priority so the write to the CMCNT counter is not performed Figure 17 6 shows the timing T1 T2 CK Address Internal write signal Compare match signal CMCNT CMCNT write cycle CMCNT N H 0000 Figure 17 6 CMCNT Write and Compare Match Contention ...

Page 635: ...the T2 state of the CMCNT counter word write cycle the counter write has priority so no increment occurs Figure 17 7 shows the timing CMCNT write data T1 T2 CK Address Internal write signal Compare match signal CMCNT CMCNT write cycle CMCNT N M Figure 17 7 CMCNT Word Write and Increment Contention ...

Page 636: ...n the writing side The byte data on the side not performing the writing is also not incremented so the contents are those before the write Figure 17 8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle T1 T2 CK Address Internal write signal CMCNT input clock CMCNTH CMCNT write cycle CMCNTH N M CMCNTH write data X X CMCNTL Figure 17 8 CMCNT Byte Write and Increm...

Page 637: ...WRHH output BSC 1 PA22 I O port WRHL output BSC 3 PA21 I O port CASHH output BSC 4 PA20 I O port CASHL output BSC 29 PA19 I O port BACK output BSC DRAK1 output DMAC 30 PA18 I O port BREQ input BSC DRAK0 output DMAC 33 PA17 O port WAIT input BSC 101 PA16 I O port AH output BSC 100 PA15 I O port CK output CPG 83 107 88 PA14 I O port RD output BSC 34 43 37 PA13 I O port WRH output BSC 36 47 39 PA12 I...

Page 638: ...EQ input BSC 30 38 33 PB6 I O port IRQ4 input INTC A18 output BSC BACK output BSC 29 37 32 PB5 I O port IRQ3 input INTC POE3 input port RDWR output BSC 28 36 29 PB4 I O port IRQ2 input INTC POE2 input port CASH output BSC 26 34 27 PB3 I O port IRQ1 input INTC POE1 input port CASL output BSC 25 32 26 PB2 I O port IRQ0 input INTC POE0 input port RAS output BSC 24 31 25 PB1 I O port A17 input BSC 22 ...

Page 639: ... PD29 I O port D29 I O BSC CS3 output BSC 56 PD28 I O port D28 I O BSC CS2 output BSC 57 PD27 I O port D27 I O BSC DACK1 output DMAC 58 PD26 I O port D26 I O BSC DACK0 output DMAC 59 PD25 I O port D25 I O BSC DREQ1 input DMAC 60 PD24 I O port D24 I O BSC DREQ0 input DMAC 62 PD23 I O port D23 I O BSC IRQ7 input INTC 64 PD22 I O port D22 I O BSC IRQ6 input INTC 65 PD21 I O port D21 I O BSC IRQ5 inpu...

Page 640: ... 66 88 71 PD3 I O port D3 I O BSC 67 89 72 PD2 I O port D2 I O BSC 68 90 73 PD1 I O port D1 I O BSC 69 91 74 PD0 I O port D0 I O BSC 70 92 75 E PE15 I O port TIOC4D I O MTU DACK1 output DMAC IRQOUT output INTC 2 5 3 PE14 I O port TIOC4C I O MTU DACK0 output DMAC AH output BSC 1 2 2 PE13 I O port TIOC4B I O MTU MRES input INTC 112 144 120 PE12 I O port TIOC4A I O MTU 111 143 119 PE11 I O port TIOC3...

Page 641: ...REQ1 input DMAC 87 111 94 PE1 I O port TIOC0B I O MTU DRAK0 output DMAC 86 110 93 PE0 I O port TIOC0A I O MTU DREQ0 input DMAC 85 109 92 F PF7 input port AN7 input A D 99 126 106 PF6 input port AN6 input A D 98 125 105 PF5 input port AN5 input A D 96 123 103 PF4 input port AN4 input A D 95 122 102 PF3 input port AN3 input A D 94 121 101 PF2 input port AN2 input A D 93 120 100 PF1 input port AN1 in...

Page 642: ...6 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 V SS PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 V SS V SS V SS PD0 D0 PD1 D1 PD2 D2 PD3 D3 PD4 D4 PD5 D5 PD6 D6 PD7 D7 PD8 D8 PD9 D9 P...

Page 643: ...KC IRQ2 PA9 TCLKD IRQ3 PA10 CS0 PA11 CS1 PA12 WRL PA13 WRH PA14 RD PA15 CK PA16 AH PA17 WAIT PA18 BREQ DRAK0 PA19 BACK DRAK1 PA20 CASHL PA21 CASHH PA22 WRHL PA23 WRHH PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS PC13 PC14 PC15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 P...

Page 644: ...PE10 TIOC3C PE11 TIOC3D PE12 TIOC4A PE13 TIOC4B MRES PE14 TIOC4C DACK0 AH PE15 TIOC4D DACK1 IRQOUT AVREF PF0 AN0 PF1 AN1 PF2 AN2 PF3 AN3 PF4 AN4 PF5 AN5 PF6 AN6 PF7 AN7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 AVREF PF0 AN0 PF1 AN1 PF2 AN2 PF3 AN3 PF4 AN4 PF5 AN5 PF6 AN6 PF7 AN7 PE0 TIOC0A PE1 TIOC0B PE2 TIOC0C PE3 TIOC0D PE4 TIOC1A PE5 TIOC1B PE6 TIOC2A PE7 TIOC2B PE8...

Page 645: ...er 2 PBCR2 R W H 0000 H FFFF839A H FFFF839B 8 16 32 Port C I O register PCIOR R W H 0000 H FFFF8396 H FFFF8397 8 16 32 Port C control register PCCR R W H 0000 H FFFF839C H FFFF839D 8 16 32 Port D I O register H PDIORH R W H 0000 H FFFF83A4 H FFFF83A5 8 16 32 Port D I O register L PDIORL R W H 0000 H FFFF83A6 H FFFF83A7 8 16 32 Port D control register H1 PDCRH1 R W H 0000 H FFFF83A8 H FFFF83A9 8 16...

Page 646: ...PAIORH bit is set to 1 and an input pin if the bit is cleared to 0 PAIORH is initialized to H 0000 by external power on reset however it is not initialized for manual resets reset by WDT standby mode or sleep mode so the previous data is maintained The settings for this register are effective only for the 144 pin version There are no corresponding pins for this register in the 112 pin and 120 pin ...

Page 647: ... 10 9 8 PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 18 3 3 Port A Control Register H PACRH PACRH is a 16 bit read write register that selects the multiplex pi...

Page 648: ...it 14 PA23MD Description 0 General input output PA23 initial value WRHH in on chip ROM invalid mode 1 Most significant byte write output WRHH PA23 in single chip mode Bit 13 Reserved This bit always reads as 0 The write value should always be 0 Bit 12 PA22 Mode PA22MD Selects the function of the PA22 WRHL pin Bit 12 PA22MD Description 0 General input output PA22 initial value WRHL in on chip ROM i...

Page 649: ... single chip mode 1 Reserved Bits 5 and 4 PA18 Mode 1 0 PA18MD1 and PA18MD0 These bits select the function of the PA18 BREQ DRAK0 pin Bit 5 PA18MD1 Bit 4 PA18MD0 Description 0 0 General input output PA18 initial value 1 Bus right request input BREQ PA18 in single chip mode 1 0 DREQ0 request received output DRAK0 PA18 in single chip mode 1 Reserved Bit 3 Reserved This bit always reads as 0 The writ...

Page 650: ... register settings that select these pin functions will be ignored depending on the operation mode Refer to table 18 2 Pin Arrangement by Mode for details PACRL1 is initialized by external power on reset to H 4000 in extended mode and to H 0000 in single chip mode PACRL2 is initialized by external power on reset to H 0000 Neither register is initialized by manual resets reset by WDT standby mode o...

Page 651: ... PA13MD Description 0 General input output PA13 initial value WRH in on chip ROM invalid mode 1 Most significant side write output WRH PA13 in single chip mode Bit 9 Reserved This bit always reads as 0 The write value should always be 0 Bit 8 PA12 Mode PA12MD Selects the function of the PA12 WRL pin Bit 8 PA12MD Description 0 General input output PA12 initial value WRL in on chip ROM invalid mode ...

Page 652: ...ese bits select the function of the PA9 TCLKD IRQ3 pin Bit 3 PA9MD1 Bit 2 PA9MD0 Description 0 0 General input output PA9 initial value 1 MTU timer clock input TCLKD 1 0 Interrupt request input IRQ3 1 Reserved Bits 1 and 0 PA8 Mode 1 0 PA8MD1 and PA8MD0 These bits select the function of the PA8 TCLKC IRQ2 pin Bit 1 PA8MD1 Bit 0 PA8MD0 Description 0 0 General input output PA8 initial value 1 MTU ti...

Page 653: ...PA7MD1 and PA7MD0 These bits select the function of the PA7 TCLKB CS3 pin Bit 15 PA7MD1 Bit 14 PA7MD0 Description 0 0 General input output PA7 initial value 1 MTU timer clock input TCLKB 1 0 Chip select output CS3 PA7 in single chip mode 1 Reserved Bits 13 and 12 PA6 Mode 1 0 PA6MD1 and PA6MD0 These bits select the function of the PA6 TCLKA CS2 pin Bit 13 PA6MD1 Bit 12 PA6MD0 Description 0 0 Gener...

Page 654: ... General input output PA4 initial value 1 Transmit data output TxD1 Bit 7 Reserved This bit always reads as 0 The write value should always be 0 Bit 6 PA3 Mode PA3MD Selects the function of the PA3 RxD1 pin Bit 6 PA3MD Description 0 General input output PA3 initial value 1 Receive data input RxD1 Bits 5 and 4 PA2 Mode 1 0 PA2MD1 and PA2MD0 These bits select the function of the PA2 SCK0 DREQ0 IRQ0 ...

Page 655: ...0IOR correspond to the PB9 IRQ7 A21 ADTRG pin to PB0 A16 pin PBIOR is enabled when the port B pins function as input outputs PB9 PB0 For other functions it is disabled For port B pin functions PB9 PB0 a given pin in port B is an output pin if its corresponding PBIOR bit is set to 1 and an input pin if the bit is cleared to 0 PBIOR is initialized to H 0000 by external power on reset however it is n...

Page 656: ...and PBCR2 are both initialized to H 0000 by external power on reset but are not initialized for manual resets reset by WDT standby mode or sleep mode so the previous data is maintained Port B Control Register 1 PBCR1 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R W R W R W R...

Page 657: ...1 10 9 8 PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD PB0MD Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R R W R R W Bits 15 and 14 PB7 Mode PB7MD1 and PB7MD0 PB7MD1 and PB7MD0 select the function of the PB7 IRQ5 A19 BREQ pin Bit 15 PB7MD1 Bit 14 PB7MD0 Descriptio...

Page 658: ...t PB5 initial value 1 Interrupt request input IRQ3 1 0 Port output enable POE3 1 Read write output RDWR Bits 9 and 8 PB4 Mode PB4MD1 and PB4MD0 PB4MD1 and PB4MD0 select the function of the PB4 IRQ2 POE2 CASH pin Bit 9 PB4MD1 Bit 8 PB4MD0 Description 0 0 General input output PB4 initial value 1 Interrupt request input IRQ2 1 0 Port output enable POE2 1 Column address strobe CASH PB4 in single chip ...

Page 659: ...s reads as 0 The write value should always be 0 Bit 2 PB1 Mode PB1MD Selects the function of the PB1 A17 pin Bit 2 PB1MD Description 0 General input output PB1 initial value A17 in on chip ROM invalid mode 1 Address output A17 PB1 in single chip mode Bit 1 Reserved This bit always reads as 0 The write value should always be 0 Bit 0 PB0 Mode PB0MD Selects the function of the PB0 A16 pin Bit 0 PA0MD...

Page 660: ... an output pin if its corresponding PCIOR bit is set to 1 and an input pin if the bit is cleared to 0 PCIOR is initialized to H 0000 by external power on reset however it is not initialized for manual resets reset by WDT standby mode or sleep mode so the previous values are maintained Bit 15 14 13 12 11 10 9 8 PC15 IOR PC14 IOR PC13 IOR PC12 IOR PC11 IOR PC10 IOR PC9 IOR PC8 IOR Initial value 0 0 ...

Page 661: ...W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PC7 MD PC6 MD PC5 MD PC4 MD PC3 MD PC2 MD PC1 MD PC0 MD Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 PC15 Mode PC15MD Selects the function of the PC15 A15 pin Bit 15 PC15MD Description 0 General input output PC15 initial value A15 in on chip ROM invalid mode 1 Address output A15 PC15 in single chip mode Bit 14 PC14 Mode PC14MD S...

Page 662: ...0 General input output PC10 initial value A10 in on chip ROM invalid mode 1 Address output A10 PC10 in single chip mode Bit 9 PC9 Mode PC9MD Selects the function of the PC9 A9 pin Bit 9 PC9MD Description 0 General input output PC9 initial value A9 in on chip ROM invalid mode 1 Address output A9 PC9 in single chip mode Bit 8 PC8 Mode PC8MD Selects the function of the PC8 A8 pin Bit 8 PC8MD Descript...

Page 663: ...ut output PC4 initial value A4 in on chip ROM invalid mode 1 Address output A4 PC4 in single chip mode Bit 3 PC3 Mode PC3MD Selects the function of the PC3 A3 pin Bit 3 PC3MD Description 0 General input output PC3 initial value A3 in on chip ROM invalid mode 1 Address output A3 PC3 in single chip mode Bit 2 PC2 Mode PC2MD Selects the function of the PC2 A2 pin Bit 2 PC2MD Description 0 General inp...

Page 664: ...en pin in port D is an output pin if its corresponding PDIORH bit is set to 1 and an input pin if the bit is cleared to 0 PDIORH is initialized to H 0000 by external power on reset however it is not initialized for manual resets reset by WDT standby mode or sleep mode so the previous data is maintained The settings for this register are effective only for the 144 pin version There are no correspon...

Page 665: ... W R W R W R W Bit 7 6 5 4 3 2 1 0 PD7 IOR PD6 IOR PD5 IOR PD4 IOR PD3 IOR PD2 IOR PD1 IOR PD0 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 18 3 11 Port D Control Registers H1 H2 PDCRH1 and PDCRH2 PDCRH1 and PDCRH2 are 16 bit read write registers that select the functions of the most significant sixteen multiplexed pins of port D PDCRH1 selects the functions of the PD31 D3...

Page 666: ...1 ADTRG pin Bit 15 PD31MD1 Bit 14 PD31MD0 Description 0 0 General input output PD31 initial value No ROM D31 with CS0 32 bit width 1 Data input output D31 PD31 in single chip mode 1 0 A D conversion trigger input ADTRG No ROM D31 with CS0 32 bit width 1 Reserved Bits 13 and 12 PD30 Mode 1 0 PD30MD1 and PD30MD0 These bits select the function of the PD30 D30 IRQOUT pin Bit 13 PD30MD1 Bit 12 PD30MD0 ...

Page 667: ...2 pin Bit 9 PD28MD1 Bit 8 PD28MD0 Description 0 0 General input output PD28 initial value D28 with no ROM and CS0 32 bit width 1 Data input output D28 PD28 in single chip mode 1 0 Chip select output CS2 PD28 in single chip mode and D28 with no ROM and CS0 32 bit width 1 Reserved Bits 7 and 6 PD27 Mode 1 0 PD27MD1 and PD27MD0 These bits select the function of the PD27 D27 DACK1 pin Bit 7 PD27MD1 Bi...

Page 668: ...D25 D25 DREQ1 pin Bit 3 PD25MD1 Bit 2 PD25MD0 Description 0 0 General input output PD25 initial value D25 with no ROM and CS0 32 bit width 1 Data input output D25 PD25 in single chip mode 1 0 DMA transfer request input DREQ1 PD25 in single chip mode and D25 with no ROM and CS0 32 bit width 1 Reserved Bits 1 and 0 PD24 Mode 1 0 PD24MD1 and PD24MD0 These bits select the function of the PD24 D24 DREQ...

Page 669: ... PD23MD0 These bits select the function of the PD23 D23 IRQ7 pin Bit 15 PD23MD1 Bit 14 PD23MD0 Description 0 0 General input output PD23 initial value D23 with no ROM and CS0 32 bit width 1 Data input output D23 PD23 in single chip mode 1 0 Interrupt request input IRQ7 1 Reserved Bits 13 and 12 PD22 Mode 1 0 PD22MD1 and PD22MD0 These bits select the function of the PD22 D22 IRQ6 pin Bit 13 PD22MD1...

Page 670: ...bits select the function of the PD20 D20 IRQ4 pin Bit 9 PD20MD1 Bit 8 PD20MD0 Description 0 0 General input output PD20 initial value D20 with no ROM and CS0 32 bit width 1 Data input output D20 PD20 in single chip mode 1 0 Interrupt request input IRQ4 1 Reserved Bits 7 and 6 PD19 Mode 1 0 PD19MD1 and PD19MD0 These bits select the function of the PD19 D19 IRQ3 pin Bit 7 PD19MD1 Bit 6 PD19MD0 Descr...

Page 671: ...ts select the function of the PD17 D17 IRQ1 pin Bit 3 PD17MD1 Bit 2 PD17MD0 Description 0 0 General input output PD17 initial value D17 with no ROM and CS0 32 bit width 1 Data input output D17 PD17 in single chip mode 1 0 Interrupt request input IRQ1 1 Reserved Bits 1 and 0 PD16 Mode 1 0 PD16MD1 and PD16MD0 These bits select the function of the PD16 D16 IRQ0 pin Bit 1 PD16MD1 Bit 0 PD16MD0 Descrip...

Page 672: ... 1 16 bit bus Port D pins are data I O pins PDCRL settings are disabled On Chip ROM Enabled Extended Mode The port D pins are shared as data I O pins and general I O pins PDCRL settings are enabled Single Chip Mode The port D pins are general I O pins PDCRL settings are disabled PDCRL is initialized to H 0000 by external power on reset but is not initialized for manual resets reset by WDT standby ...

Page 673: ...ut PD13 initial value D13 in on chip ROM invalid mode 1 Data input output D13 PD13 in single chip mode Bit 12 PD12 Mode PD12MD Selects the function of the PD12 D12 pin Bit 12 PD12MD Description 0 General input output PD12 initial value D12 in on chip ROM invalid mode 1 Data input output D12 PD12 in single chip mode Bit 11 PD11 Mode PD11MD Selects the function of the PD11 D11 pin Bit 11 PD11MD Desc...

Page 674: ...output PD7 initial value D7 in on chip ROM invalid mode 1 Data input output D7 PD7 in single chip mode Bit 6 PD6 Mode PD6MD Selects the function of the PD6 D6 pin Bit 6 PD6MD Description 0 General input output PD6 initial value D6 in on chip ROM invalid mode 1 Data input output D6 PD6 in single chip mode Bit 5 PD5 Mode PD5MD Selects the function of the PD5 D5 pin Bit 5 PD5MD Description 0 General ...

Page 675: ...output PD2 initial value D2 in on chip ROM invalid mode 1 Data input output D2 PD2 in single chip mode Bit 1 PD1 Mode PD1MD Selects the function of the PD1 D1 pin Bit 1 PD1MD Description 0 General input output PD1 initial value D1 in on chip ROM invalid mode 1 Data input output D1 PD1 in single chip mode Bit 0 PD0 Mode PD0MD Selects the function of the PD0 D0 pin Bit 0 PD0MD Description 0 General ...

Page 676: ...PE11 IOR PE10 IOR PE9 IOR PE8 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PE7 IOR PE6 IOR PE5 IOR PE4 IOR PE3 IOR PE2 IOR PE1 IOR PE0 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 18 3 14 Port E Control Registers 1 2 PECR1 and PECR2 PECR1 and PECR2 are 16 bit read write registers that select the functions of the sixteen multiple...

Page 677: ...5 PE15MD1 Bit 14 PE15MD0 Description 0 0 Input output PE15 initial value 1 MTU input capture input output compare output TIOC4D 1 0 DMAC request received output DACK1 PE15 in single chip mode 1 Interrupt request output IRQOUT Reserved in single chip mode Bits 13 and 12 PE14 Mode 1 0 PE14MD1 and PE14MD0 These bits select the function of the PE14 TIOC4C DACK0 AH pin Bit 13 PE14MD1 Bit 12 PE14MD0 Des...

Page 678: ... PE12 initial value 1 MTU input capture input output compare output TIOC4A Bit 7 Reserved This bit always reads as 0 The write values should always be 0 Bit 6 PE11 Mode PE11MD Selects the function of the PE11 TIOC3D pin Bit 6 PE11MD Description 0 General input output PE11 initial value 1 MTU input capture input output compare output TIOC3D Bit 5 Reserved This bit always reads as 0 The write values...

Page 679: ...ut TIOC3A Port E Control Register 2 PECR2 Bit 15 14 13 12 11 10 9 8 PE7MD PE6MD PE5MD PE4MD Initial value 0 0 0 0 0 0 0 0 R W R R W R R W R R W R R W Bit 7 6 5 4 3 2 1 0 PE3 MD1 PE3 MD0 PE2 MD1 PE2 MD0 PE1 MD1 PE1 MD0 PE0 MD1 PE0 MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 Reserved This bit always reads as 0 The write value should always be 0 Bit 14 PE7 Mode PE7MD ...

Page 680: ...pture input output compare output TIOC1B Bit 9 Reserved This bit always reads as 0 The write value should always be 0 Bit 8 PE4 Mode PE4MD Selects the function of the PE4 TIOC1A pin Bit 8 PE4MD Description 0 General input output PE4 initial value 1 MTU input capture input output compare output TIOC1A Bits 7 and 6 PE3 Mode 1 0 PE3MD1 and PE3MD0 These bits select the function of the PE3 TIOC0D DRAK1...

Page 681: ...IOC0B 1 0 DREQ0 request received output DRAK0 PE1 in single chip mode 1 Reserved Bits 1 and 0 PE0 Mode 1 0 PE0MD1 and PE0MD0 These bits select the function of the PE0 TIOC0A DREQ0 pin Bit 1 PE0MD1 Bit 0 PE0MD0 Description 0 0 General input output PE0 initial value 1 MTU input capture input output compare output TIOC0A 1 0 DREQ0 request receive input PE0 in single chip mode 1 Reserved 18 3 15 IRQOU...

Page 682: ... writes are also possible in the 112 pin and 120 pin versions but they have no effect on the pin functions Bit 3 IRQMD3 Bit 2 IRQMD2 Description 0 0 Interrupt request received output initial value 1 Refresh signal output 1 0 Interrupt request received or refresh signal output which of the two is output depends on the operation status at the time 1 Always high level output Bits 1 and 0 IRQOUT Mode ...

Page 683: ...645 18 4 Cautions on Use For the I O ports and pins with multiplexing of DREQ or IRQ switching from the port input Low level condition to IRQ or DREQ edge detection will detect the concerned edge ...

Page 684: ...646 ...

Page 685: ... controller PFC to select the function of multiplexed pins The ports each have one data register for storing pin data The initialize function after power on reset differs depending on the operating mode of each pin See table 18 2 Pin Arrangement by Mode for details 19 2 Port A There are two versions of port A FP 112 TFP 120 FP 144 In the FP 112 and TFP 120 versions port A is a 16 pin input output ...

Page 686: ...2 input PA8 I O TCLKC input IRQ2 input PA7 I O TCLKB input CS3 output PA7 I O TCLKB input CS3 output PA7 I O TCLKB input PA6 I O TCLKA input CS2 output PA6 I O TCLKA input CS2 output PA6 I O TCLKA input PA5 I O SCK1 I O DREQ1 input IRQ1 input PA5 I O SCK1 I O DREQ1 input IRQ1 input PA5 I O SCK1 I O IRQ1 input PA4 I O TXD1 output PA4 I O TXD1 output PA4 I O TXD1 output PA3 I O RXD1 input PA3 I O RX...

Page 687: ... PA12 I O WRL output PA12 I O CS1 output PA11 I O CS1 output PA11 I O CS0 output PA10 I O CS0 output PA10 I O PA9 I O TCLKD input IRQ3 input PA9 I O TCLKD input IRQ3 input PA9 I O TCLKD input IRQ3 input PA8 I O TCLKC input IRQ2 input PA8 I O TCLKC input IRQ2 input PA8 I O TCLKC input IRQ2 input PA7 I O TCLKB input CS3 output PA7 I O TCLKB input CS3 output PA7 I O TCLKB input PA6 I O TCLKA input CS...

Page 688: ...in status When the pins are used as ordinary inputs the pin status rather than the register value is read directly when PADRH is read When a value is written to PADRH that value can be written into PADRH but it will not affect the pin status Table 19 4 shows the read write operations of the port A data register PADRH is initialized by an external power on reset However PADRH is not initialized for...

Page 689: ...port A data register PADRL is initialized by an external power on reset However PADRL is not initialized for manual reset reset by WDT standby mode or sleep mode Bit 15 14 13 12 11 10 9 8 PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value 0 0 0 0 0 ...

Page 690: ... input PB6 I O IRQ4 input PB5 I O IRQ3 input POE3 input RDWR output PB5 I O IRQ3 input POE3 input RDWR output PB5 I O IRQ3 input POE3 input PB4 I O IRQ2 input POE2 input CASH output PB4 I O IRQ2 input POE2 input CASH output PB4 I O IRQ2 input POE2 input PB3 I O IRQ1 input POE1 input CASL output PB3 I O IRQ1 input POE1 input CASL output PB3 I O IRQ1 input POE1 input PB2 I O IRQ0 input POE0 input RA...

Page 691: ...d write operations of the port B data register PBDR is initialized by an external power on reset However PBDR is not initialized for a manual reset reset by WDT standby mode or sleep mode Bit 15 14 13 12 11 10 9 8 PB9DR PB8DR Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R W R W Bit 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R ...

Page 692: ... A10 output PC10 I O A9 output PC9 I O A9 output PC9 I O A8 output PC8 I O A8 output PC8 I O A7 output PC7 I O A7 output PC7 I O A6 output PC6 I O A6 output PC6 I O A5 output PC5 I O A5 output PC5 I O A4 output PC4 I O A4 output PC4 I O A3 output PC3 I O A3 output PC3 I O A2 output PC2 I O A2 output PC2 I O A1 output PC1 I O A1 output PC1 I O A0 output PC0 I O A0 output PC0 I O 19 4 1 Register Con...

Page 693: ... data register PCDR is initialized by an external power on reset However PCDR is not initialized for a manual reset reset by WDT standby mode or sleep mode Bit 15 14 13 12 11 10 9 8 PC15DR PC14DR PC13DR PC12DR PC11DR PC10DR PC9DR PC8DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value 0 0 0 0 0 0 0 0 ...

Page 694: ...I O D13 I O PD13 I O D12 I O D12 I O PD12 I O D12 I O PD12 I O D11 I O D11 I O PD11 I O D11 I O PD11 I O D10 I O D10 I O PD10 I O D10 I O PD10 I O D9 I O D9 I O PD9 I O D9 I O PD9 I O D8 I O D8 I O PD8 I O D8 I O PD8 I O D7 I O D7 I O PD7 I O D7 I O PD7 I O D6 I O D6 I O PD6 I O D6 I O PD6 I O D5 I O D5 I O PD5 I O D5 I O PD5 I O D4 I O D4 I O PD4 I O D4 I O PD4 I O D3 I O D3 I O PD3 I O D3 I O PD...

Page 695: ...6 I O PD25 I O D25 I O DREQ1 input D25 I O PD25 I O D25 I O DREQ1 input PD25 I O PD24 I O D24 I O DREQ0 input D24 I O PD24 I O D24 I O DREQ0 input PD24 I O PD23 I O D23 I O IRQ7 input D23 I O PD23 I O D23 I O IRQ7 input PD23 I O IRQ7 input PD22 I O D22 I O IRQ6 input D22 I O PD22 I O D22 I O IRQ6 input PD22 I O IRQ6 input PD21 I O D21 I O IRQ5 input D21 I O PD21 I O D21 I O IRQ5 input PD21 I O IRQ...

Page 696: ... PD9 I O D8 I O D8 I O PD8 I O D8 I O PD8 I O D7 I O D7 I O PD7 I O D7 I O PD7 I O D6 I O D6 I O PD6 I O D6 I O PD6 I O D5 I O D5 I O PD5 I O D5 I O PD5 I O D4 I O D4 I O PD4 I O D4 I O PD4 I O D3 I O D3 I O PD3 I O D3 I O PD3 I O D2 I O D2 I O PD2 I O D2 I O PD2 I O D1 I O D1 I O PD1 I O D1 I O PD1 I O D0 I O D0 I O PD0 I O D0 I O PD0 I O 19 5 1 Register Configuration Table 19 13 summarizes the p...

Page 697: ... be written into PDDRH but it will not affect the pin status Table 19 14 shows the read write operations of the port D data register PDDRH is initialized by an external power on reset However PDDRH is not initialized for a manual reset reset by WDT standby mode or sleep mode These register settings function only for the 144 pin version There are no pins corresponding to this register in the 112 pi...

Page 698: ...t D data register PDDRL is initialized by an external power on reset However PDDRL is not initialized for a manual reset reset by WDT standby mode or sleep mode Bit 15 14 13 12 11 10 9 8 PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR PD8DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial value 0 0 0 0 0 0...

Page 699: ...C3C I O PE9 I O TIOC3B I O PE9 I O TIOC3B I O PE8 I O TIOC3A I O PE8 I O TIOC3A I O PE7 I O TIOC2B I O PE7 I O TIOC2B I O PE6 I O TIOC2A I O PE6 I O TIOC2A I O PE5 I O TIOC1B I O PE5 I O TIOC1B I O PE4 I O TIOC1A I O PE4 I O TIOC1A I O PE3 I O TIOC0D I O DRAK1 output PE3 I O TIOC0D I O PE2 I O TIOC0C I O DREQ1 input PE2 I O TIOC0C I O PE1 I O TIOC0B I O DRAK0 output PE1 I O TIOC0B I O PE0 I O TIOC...

Page 700: ...ta register PEDR is initialized by a external power on reset However PEDR is not initialized for a manual reset reset by WDT standby mode or sleep mode so the previous data is retained Bit 15 14 13 12 11 10 9 8 PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR I...

Page 701: ...rt F The bits PF7DR PF0DR correspond to the PF7 AN7 PF0 AN0 pins There are no bits 15 8 so always access as eight bits Any value written into these bits is ignored and there is no effect on the status of the pins When any of the bits are read the pin status rather than the bit value is read directly However when an A D converter analog input is being sampled values of 1 are read out Table 19 19 sh...

Page 702: ... Read Write Operation of the Port F Data Register PFDR Pin I O Pin Function Read Write Input Ordinary Pin status is read Ignored no effect on pin status ANn analog input 1 is read Ignored no effect on pin status n 7 0 ...

Page 703: ... controller DTC through a 32 bit data bus figures 20 1 20 2 and 20 3 The CPU DMAC and DTC can access the on chip ROM in 8 16 and 32 bit widths Data in the on chip ROM can always be accessed in one cycle H 00000000 H 00000004 H 00000001 H 00000005 H 00000002 H 00000006 H 00000003 H 00000007 H 0000FFFC H 0000FFFD H 0000FFFE H 0000FFFF On chip ROM Internal data bus 32 bits Figure 20 1 Mask ROM Block ...

Page 704: ... H 0001FFFF On chip ROM Internal data bus 32 bits Figure 20 2 Mask ROM Block Diagram 128 kbyte Version H 00000000 H 00000004 H 00000001 H 00000005 H 00000002 H 00000006 H 00000003 H 00000007 H 0003FFFC H 0003FFFD H 0003FFFE H 0003FFFF On chip ROM Internal data bus 32 bits Figure 20 3 Mask ROM Block Diagram 256 kbyte Version ...

Page 705: ... 128 kbyte version and H 00000000 H 0003FFFF of memory area 0 for the 256 kbyte version Table 20 1 Operation Modes and ROM Mode Setting Pin Operation Mode MD3 MD2 MD1 MD0 Area 0 Mode 0 MCU mode 0 0 0 On chip ROM invalid external 8 bit space 112 pin and 120 pin external 16 bit space 144 pin Mode 1 MCU mode 1 0 1 On chip ROM invalid external 16 bit space 112 pin and 120 pin external 32 bit space 144...

Page 706: ...668 ...

Page 707: ...accessed in one cycle H 00000000 H 00000004 H 00000001 H 00000005 H 00000002 H 00000006 H 00000003 H 00000007 H 0001FFFC H 0001FFFD H 0001FFFE H 0001FFFF On chip ROM Internal data bus 32 bits Figure 21 1 PROM Block Diagram The operating mode determines whether the on chip ROM is valid or not The operating mode is selected using mode setting pins MD3 MD0 as shown in table 21 1 If you are using the ...

Page 708: ...to section 3 Operating Modes With the PROM version programs can be written in the same manner as with an ordinary EPROM by setting the LSI to PROM mode and using a standard EPROM writer 21 2 PROM Mode 21 2 1 PROM Mode Settings When programming the on chip PROM set the pins as shown in figure 21 2 21 3 or 21 4 and perform the programming in PROM mode 21 2 2 Socket Adapter Pin Correspondence and Mem...

Page 709: ...LVSS EXTAL 81 82 74 VSS AVSS 3 23 27 33 39 55 61 71 90 101 109 MD1 79 78 MD2 75 MD3 73 97 PF0 AN0 PF7 AN7 91 96 98 99 26 PE15 TIOC4D DACK1 IRQOUT PE14 TIOC4C DACK0 AH 2 PB5 IRQ3 POE3 RDWR 1 28 Pin number Pin name 1 VPP 26 A9 13 I O0 14 I O1 15 I O2 17 I O3 18 I O4 19 I O5 20 I O6 21 I O7 12 A0 11 A1 10 A2 9 A3 8 A4 7 A5 6 A6 5 27 A7 24 A8 23 OE 25 A10 4 A11 A12 28 29 A13 3 A14 A15 2 31 A16 PGM 22 ...

Page 710: ... IRQOUT PE14 TIOC4C DACK0 AH PB5 IRQ3 POE3 RDWR VCC MD0 MD1 MD2 PLLVCC AVCC PLLCAP PLLVSS EXTAL VSS PF0 AN0 to PF5 AN5 PF6 AN6 to PF7 AN7 AVSS MD3 Pin name Pin number Vpp 1 A9 26 I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 A15 A16 PGM CE Vcc Vss 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 3 2 31 22 32 16 SH7042 120 pin version HN27C1...

Page 711: ...VSS AVSS 6 14 28 35 42 55 61 71 79 87 93 117 129 141 MD1 103 102 MD2 97 MD3 95 124 PF0 AN0 PF7 AN7 118 123 125 126 34 PE15 TIOC4D DACK1 IRQOUT PE14 TIOC4D DACK0 AH 5 PB5 IRQ3 POE3 RDWR 2 36 Pin number Pin name 1 VPP 26 A9 13 I O0 14 I O1 15 I O2 17 I O3 18 I O4 19 I O5 20 I O6 21 I O7 12 A0 11 A1 10 A2 9 A3 8 A4 7 A5 6 A6 5 27 A7 24 A8 23 OE 25 A10 4 A11 A12 28 29 A13 3 A14 A15 2 31 A16 PGM 22 32 ...

Page 712: ...rs that only support page programming mode cannot be used When selecting a PROM writer confirm that it supports the byte by byte high speed high reliability programming format 21 3 1 Programming Mode Selection There are two on chip PROM programming modes write and verify reads and confirms written data The mode is selected by using the pins table 21 2 Table 21 2 PROM Programming Mode Selection Pin...

Page 713: ...rification can be done using an efficient high speed high reliability programming format This format allows data writing that is both fast and reliable without applying voltage stress to the device Figure 21 6 shows the basic flow of the high speed high reliability programming format ...

Page 714: ...result OK No Yes Final address No Yes Set EPROM writer to read mode VCC 5 0 V 0 25 V VPP VCC All address read results OK No Yes End No good No VCC Power supply VPP PROM program power supply tPW Initial programming pulse width tOPW Over programming pulse width n 25 Yes Address 1 address Preliminary Figure 21 6 High Speed High Reliability Programming Basic Flow ...

Page 715: ...tem Pin Symbol Min Typ Max Unit Measurement Conditions Input high level voltage I O7 I O0 A16 A0 OE CE PGM VIH 2 4 VCC 0 3 V Input low level voltage I O7 I O0 A16 A0 OE CE PGM VIL 0 3 0 8 V Output high level voltage I O7 I O0 VOH 2 4 V IOH 200 µA Output low level voltage I O7 I O0 VOL 0 45 V IOL 1 6 mA Input leak current I O7 I O0 A16 A0 OE CE PGM ILI 2 µA VIN 5 25 V 0 5 V VCC current ICC 80 mA VP...

Page 716: ...µs PGM pulse width during initial programming tPW 0 19 0 20 0 21 ms PGM pulse width during over programming tOPW 3 0 19 5 25 ms Vcc setup time tVCS 2 µs CE setup time tCES 2 µs Data output delay time tOE 0 150 ns Notes 1 Input pulse level 0 45 V to 2 4 V input rise fall times 20 ns input timing reference levels 0 8 V 2 0 V output timing reference levels 0 8 V 2 0 V 2 tDF is defined as when the out...

Page 717: ...hi specifications VPP becomes 12 5 V Devices will sometimes be destroyed if a voltage higher than the rated one is applied Pay particular attention to such phenomena as EPROM writer overshoot 2 Always confirm that the indices of the EPROM writer socket socket adapter and device are in agreement before programming Devices will sometimes be destroyed due to excessive current flow if these are not co...

Page 718: ...ve the data retention characteristics High temperature biasing is a method of screening that eliminates parts with faulty initial data retention by on chip PROM memory cells within a short period of time Figure 21 8 shows the flow from the on chip PROM programming including screening to the installation of the device on a board Program write verify Installation on board Figure 21 5 flowchart Unpow...

Page 719: ... is 100 ms typ per block Reprogramming capability The flash memory can be reprogrammed up to 100 times On board programming modes There are two modes in which flash memory can be programmed erased verified on board Boot mode User program mode Automatic bit rate adjustment With data transfer in boot mode this LSI s bit rate can be automatically adjusted to match the transfer bit rate of the host Fl...

Page 720: ...t Module bus Bus interface controller Operation mode FWP pin Mode pins Flash memory 256kB Legend FLMCR1 Flash memory control register 1 FLMCR2 Flash memory control register 2 EBR1 Block specification register 1 EBR2 Block specification register 2 RAMER RAM emulation register Figure 22 1 Flash Memory Block Diagram ...

Page 721: ... can be programmed and erased in boot mode user program mode and programmer mode MD1 0 FWP 0 RES 0 RES 0 FWP 0 FWP 1 1 1 2 M D 1 1 F W P 0 R E S 0 MD1 1 FWP 1 RES 0 Notes Execute transition between the user mode and user program mode while the CPU is not programming or erasing the flash memory 1 RAM emulation permitted 2 MD0 1 MD1 0 MD2 1 MD3 1 Reset state User mode User program mode Boot mode Pro...

Page 722: ...ed regardless of blocks 4 Writing the new application program Execute the program transferred to RAM from the host and write the new application program located at the transfer destination to the flash memory Erasing the flash memory New application program Program execution state 1 Initial state The old program version or data remains written in the flash memory The user should prepare the progra...

Page 723: ...ng control program Programming control program Programming control program Program execution state New application program Flash memory erase 4 Writing new application program Next the new application program in the host is written into the erased flash memory blocks Do not write to unerased blocks 1 Initial state The FWP assessment program that confirms that user program mode has been entered and...

Page 724: ...RAM Flash memory Application program Emulation block Overlap RAM Emulation is executed using data written to RAM SCI Figure 22 5 Emulation When overlap RAM data is confirmed the RAMS bit is cleared RAM overlap is released and writes should actually be performed to the flash memory When the programming control program is transferred to RAM ensure that the transfer destination and the overlap RAM do...

Page 725: ...ng to the Flash Memory 22 2 5 Differences between Boot Mode and User Program Mode Table 22 1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program 2 1 2 3 1 Erase erase verify 2 Program program verify 3 Emulation Note To be prepared by the user according to the recommended algorithm ...

Page 726: ...y is divided into seven 32 kbyte blocks one 28 kbyte blocks and four 1 kbyte blocks Address H 00000 Address H 3FFFF 32kbyte 32kbyte 256kbyte 32kbyte 28kbyte 1kbyte 1kbyte 1kbyte 1kbyte 32kbyte 32kbyte 32kbyte 32kbyte Figure 22 7 Block Configuration ...

Page 727: ...ntrol register 2 FLMCR2 R W 1 H 00 3 H FFFF8581 8 Erase block register 1 EBR1 R W 1 H 00 3 H FFFF8582 8 Erase block register 2 EBR2 R W 1 H 00 3 H FFFF8583 8 RAM emulation register RAMER R W H 0000 H FFFF8628 8 16 32 Notes 1 FLMCR1 FLMCR2 EBR1 and EBR2 are 8 bit registers and RAMER is a 16 bit register 2 Only byte accesses are valid for FLMCR1 FLMCR2 EBR1 and EBR2 the access requiring 3 cycles Thr...

Page 728: ...s are invalid Writes to bits SWE ESU1 PSU1 EV1 and PV1 are enabled only when FWE 1 and SWE 1 writes to the E1 bit only when FWE 1 SWE 1 and ESU1 1 and writes to the P1 bit only when FWE 1 SWE 1 and PSU1 1 Bit 7 6 5 4 3 2 1 0 FWE SWE ESU1 PSU1 EV1 PV1 E1 P1 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bit 7 Flash Write Enable Bit FWE Displays the state of the FWP pin which sets h...

Page 729: ...e Verify 1 EV1 Selects erase verify mode transition or release applicable addresses H 00000 H 1FFFF Do not set the SWE ESU1 PSU1 PV1 E1 or P1 bit at the same time Bit 3 EV1 Description 0 Erase verify mode release Initial value 1 Transition to erase verify mode Setting condition When FWE 1 and SWE 1 Bit 2 Program Verify 1 PV1 Selects program verify mode transition or release applicable addresses H ...

Page 730: ...red by setting SWE FLMCR1 to 1 when FWE FLMCR1 1 then setting the EV2 or PV2 bit Program mode for addresses H 20000 H 3FFFF is entered by setting SWE FLMCR1 to 1 when FWE FLMCR1 1 then setting the PSU2 bit and finally setting the P2 bit Erase mode for addresses H 20000 H 3FFFF is entered by setting SWE FLMCR1 to 1 when FWE FLMCR1 1 then setting the ESU2 bit and finally setting the E2 bit FLMCR2 is...

Page 731: ...y program erase protect error protect enabled Setting condition See section 22 8 3 Error protection Bit 6 Reserved bit This bit is always read as 0 Bit 5 Erase Setup Bit 2 ESU2 Prepares for a transition to erase mode applicable addresses H 20000 H 3FFFF Do not set the PSU2 EV2 PV2 E2 or P2 bit at the same time Bit 5 ESU2 Description 0 Erase setup release Initial value 1 Erase setup Setting conditi...

Page 732: ...n 0 Program verify mode release Initial value 1 Transition to the program verify mode Setting condition When FWE 1 and SWE 1 Bit 1 Erase 2 E2 Selects erase mode transition or release applicable addresses H 20000 H 3FFFF Do not set the ESU2 PSU2 EV2 PV2 or P2 bit at the same time Bit 1 E2 Description 0 Erase mode release Initial value 1 Transition to the erase mode Setting condition When FWE 1 SWE ...

Page 733: ...writes are invalid The flash memory block configuration is shown in table 22 4 Bit 7 6 5 4 3 2 1 0 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R W R W R W R W 22 5 4 Erase Block Register 2 EBR2 EBR2 is an 8 bit register that specifies the flash memory erase area block by block EBR2 is initialized to H 00 by a power on reset and standby mode when a high level is input to the FWP pin a...

Page 734: ...ing RAMER is initialized to H 0000 by a power on reset It is not initialized in software standby mode RAMER settings should be made in user mode or user program mode For details see the description of the BSC Flash memory area divisions are shown in table 22 5 To ensure correct operation of the emulation function the ROM for which RAM emulation is performed should not be accessed immediately after...

Page 735: ...disabled Initial value 1 Emulation selected Program erase protect of all flash memory blocks is enabled Bits 1 and 0 Flash Memory Area Selection RAM1 RAM0 These bits are used together with bit 2 to select the flash memory area to be overlapped with RAM See table 22 5 Table 22 5 Separation of the Flash Memory Area Addresses Block Name RAMS RAM1 RAM0 H FFF800 H FFFBFF RAM area 1kB 0 H 03F000 H 03F3F...

Page 736: ... transition to each of these modes are shown in table 22 6 For a diagram of the transitions to the various flash memory modes see figure 22 2 Table 22 6 Setting On Board Programming Modes Mode PLL Multiple FWP MD3 MD2 MD1 MD0 Boot mode Expanded Mode 1 0 0 0 0 0 Single chip Mode 0 0 0 1 Expanded Mode 2 0 1 0 0 Single chip Mode 0 1 0 1 Expanded Mode 4 1 0 0 0 Single chip Mode 1 0 0 1 User program mo...

Page 737: ...m received via SCI channel 1 is written into the programming control program area in on chip RAM After the transfer is completed control branches to the start address of the programming control program area and the programming control program execution state is entered flash memory programming is performed The transferred programming control program must therefore include coding that follows the p...

Page 738: ...completion of bit rate adjustment is received then transmits 1 byte of data H 55 After receiving H 55 this LSI sends 1 byte of H AA The host sends the byte number N of the user program in sequence of upper byte then lower byte This LSI sends the received byte number to the host as verify data echo back The host transmits the user program in sequence using byte units This LSI sends the received pro...

Page 739: ...on H 00 has been received normally and transmit one H 55 byte to the LSI If reception cannot be performed normally initiate boot mode again reset and repeat the above operations Depending on the host s transmission bit rate and the LSI s system clock frequency there will be a discrepancy between the bit rates of the host and the LSI To ensure correct SCI operation the host s transfer bit rate shou...

Page 740: ... mode switches to the programming control program transferred from the host Boot program area 2k bytes Programming control program area 2k bytes H FFFFF000 H FFFFF800 H FFFFFFFF Figure 22 11 RAM Areas in Boot Mode Note The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM Note also that the boot program remains...

Page 741: ... flash memory rewriting Transfer programming erase control program to RAM FWP 1 user program mode Write FWP assessment program and transfer program 1 2 3 4 5 Figure 22 12 User Program Mode Execution Procedure Notes 1 When programming and erasing start the watchdog timer so that measures can be taken to prevent program runaway etc Memory cells may not operate normally if overprogrammed or overerase...

Page 742: ...Mode n 1 for Addresses H 0000 H 1FFFF n 2 for Addresses H 20000 H 3FFFF When writing data or programs to flash memory the program program verify flowchart shown in figure 22 13 should be followed Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability...

Page 743: ...n FLMCRn Before reading in program verify mode a dummy write of H FF data should be made to the addresses to be read The dummy write should be executed after the elapse of 4 µs or more When the flash memory is read in this state verify data is read in 32 bit units the data at the latched address is read Wait at least 2 µs after the dummy write before performing this read operation Next the written...

Page 744: ...m data and a 32 byte area for storing reprogram data are required in RAM The contents of the latter are rewritten according to the progress of the programming operation 5 Make sure to set the wait times and repetitions as specified Programming may not complete correctly if values other than the specified ones are used Start RAM Program data storage area 32 bytes Reprogram data storage area 32 byte...

Page 745: ... R0 3 8 13 Work registers FLMCR1 EQU H 80 FLMCR2 EQU H 81 OK EQU H 0 NG EQU H 1 Wait10u EQU 72 Wait50u EQU 359 Wait4u EQU 29 Wait2u EQU 14 Wait200u EQU 1435 WDT_TCSR EQU H FFFF8610 WDT_573u EQU H A579 SWESET EQU B 01000000 PSU1SET EQU B 00010000 P1SET EQU B 00000001 P1CLEAR EQU B 11111110 PSU1CLEAR EQU B 11101111 PVSET EQU B 00000100 PVCLEAR EQU B 11111011 SWECLEAR EQU B 10111111 MAXVerify EQU 100...

Page 746: ...SUBC R2 R3 Wait 10 µs BF Wait_1 MOV L H 20000 R9 CMP GT R5 R9 BT Program_Start MOV L FLMCR2 R0 Program_Start EQU MOV L 0 R9 Initialize n R9 to 0 Program_loop EQU MOV L 0 R10 Initialize m R10 to 0 MOV L 32 R3 Write 32 byte data consecutively MOV L PdataBuff R12 MOV L R5 R13 Write_Loop EQU MOV B R12 R1 MOV B R1 R13 ADD L 1 R13 ADD L 1 R3 CMP PL R3 BT Write_Loop MOV L WDT_TCSR R1 Enable WDT MOV W WDT...

Page 747: ... Wait10u R3 AND B P1CLEAR R0 GBR Clear P Wait_4 SUBC R2 R3 Wait 10 µs BF Wait_4 MOV L Wait10u R3 AND B PSU1CLEAR R0 GBR Clear PSU Wait_5 SUBC R2 R3 Wait 10 µs BF Wait_5 MOV L WDT_TCSR R1 Disable WDT MOV W H A55F R3 MOV W R3 R1 MOV L Wait4u R3 OR B PVSET R0 GBR Set PV Wait_6 SUBC R2 R3 Wait 4 µs BF Wait_6 MOV L PdataBuff R3 MOV L R4 R1 MOV L R5 R12 MOV L 8 R13 MOV L H FFFFFFFF R11 ...

Page 748: ...XOR R8 R7 Program data computation NOT R7 R7 OR R7 R8 MOV L R8 R3 Store in reprogram data RAM PdataBuff Verify_OK EQU ADD L 4 R3 ADD L 1 R13 CMP PL R13 BT VerifyLoop MOV L Wait4u R7 AND B PVCLEAR R0 GBR Clear PV Wait_8 SUBC R2 R7 Wait 4 µs BF Wait_8 CMP PL R10 if m 0 then GOTO Program_OK BF Program_OK ADD 1 R9 MOV L NG R7 R7 NG return value MOV L MAXVerify R12 if n MAXVerify then Program NG CMP EQ...

Page 749: ... SWE bit to 1 in flash memory control register 1 FLMCR1 Next the watchdog timer is set to prevent overerasing in the event of program runaway etc Set 5 3 µs as the WDT overflow period After this preparation for erase mode erase setup is carried out by setting the ESUn bit in FLMCRn and after the elapse of 200 µs or more the operating mode is switched to erase mode by setting the En bit in FLMCRn T...

Page 750: ...ad in this state verify data is read in 32 bit units the data at the latched address is read Wait at least 2 µs after the dummy write before performing this read operation If the read data has been erased all 1 a dummy write is performed to the next address and erase verify is performed If the read data is unerased set erase mode again and repeat the erase erase verify sequence in the same way How...

Page 751: ...SWE bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n 60 NG NG NG NG OK OK OK OK n n 1 Increment address Notes 1 Preprogramming setting erase block data to all 0 is not necessary 2 Verify data is read in 32 bit longword units 3 Set only one bit in EBR1 2 More than one bit cannot be set 4 Erasing...

Page 752: ...sed R5 input Memory block table pointer R7 output OK normal or NG error R0 3 6 8 9 Work registers FLMCR1 EQU H 80 FLMCR2 EQU H 81 EBR1 EQU H 82 EBR2 EQU H 83 Wait10u EQU 72 Wait2u EQU 14 Wait200u EQU 1435 Wait5m EQU 35875 Wait20u EQU 144 Wait5u EQU 36 WDT_TCSR EQU H FFFF8610 WDT_9m EQU H A57D SWESET EQU B 01000000 ESUSET EQU B 00100000 ESET EQU B 00000010 ECLEAR EQU B 11111101 ESUCLEAR EQU B 11011...

Page 753: ...2 GBR Erase memory block EBR2 setting MOV L FLMCR1 R0 MOV L R5 R6 Erase memory block start address R6 MOV L H 020000 R7 CMP GT R6 R7 BT EraseLoop MOV L FLMCR2 R0 EraseLoop EQU MOV L WDT_TCSR R1 Enable WDT MOV W WDT_9m R3 9 2 ms cycle MOV W R3 R1 MOV L Wait200u R3 OR B ESUSET R0 GBR Set ESU EWait_2 SUBC R2 R3 Wait 200 µs BF EWait_2 MOV L Wait5m R3 OR B ESET R0 GBR Set E EWait_3 SUBC R2 R3 Wait 5 ms...

Page 754: ...GBR Set EV EWait_6 SUBC R2 R3 Wait 20 µs BF EWait_6 MOV L R5 R6 Erase memory block start address R6 BlockVerify_1 EQU Erase verify MOV L H FFFFFFFF R8 MOV L R8 R6 H FF dummy write MOV L Wait2u R3 EWait_7 SUBC R2 R3 BF EWait_7 MOV L R6 R1 Read verify data CMP EQ R8 R1 BF BlockVerify_NG MOV L 8 R5 R7 CMP EQ R6 R7 Check for last address of memory block BF BlockVerify_1 MOV L Wait5u R3 AND B EVCLEAR R...

Page 755: ... B SWECLEAR R0 GBR Clear SWE RTS NOP Memory block table Memory block start address EBR value ALIGN 4 Flash_BlockData EQU EB0 DATA L H 00000000 H 00000100 EB1 DATA L H 00008000 H 00000200 EB2 DATA L H 00010000 H 00000400 EB3 DATA L H 00018000 H 00000800 EB4 DATA L H 00020000 H 00000001 EB5 DATA L H 00028000 H 00000002 EB6 DATA L H 00030000 H 00000004 EB7 DATA L H 00038000 H 00000008 EB8 DATA L H 00...

Page 756: ... protected state See table 22 8 Table 22 8 Hardware Protection Function Item Description Program Erase FWP pin protection When a high level is input to the FWP pin FLMCR1 FLMCR2 EBR1 and EBR2 are initialized and the program erase protected state is entered Yes Yes Reset standby protection In a reset including a WDT overflow reset and in standby mode FLMCR1 FLMCR2 EBR1 and EBR2 are initialized and ...

Page 757: ...software protect transition cannot be made to the program mode or the erase mode even when setting P1 or E1 bits of the flash memory control register 1 FLMCR1 or P2 or E2 bits of flash memory control register 2 FLMCR2 See table 22 9 Table 22 9 Software Protection Function Item Description Program Erase SWE bit protection Clearing the SWE bit to 0 in FLMCR1 sets the program erase protected state fo...

Page 758: ... but program mode or erase mode is aborted at the point at which the error occurred Program mode or erase mode cannot be re entered by re setting the P1 P2 E1 or E2 bit However PV1 PV2 EV1 and EV2 bit setting is enabled and a transition can be made to verify mode FLER bit setting conditions are as follows 1 When flash memory is read during programming erasing including a vector read or instruction...

Page 759: ...1 EBR2 initialization state Error protection mode software standby Software standby mode release RD Memory read possible VF Verify read possible PR Programming possible ER Erase enable RD Memory read not possible VF Verify read not possible PR Programming not possible ER Erasing not possible Legend Error protection mode FLMCR1 FLMCR2 EBR1 EBR2 initialization state Figure 22 15 Flash Memory State T...

Page 760: ...ccesses can be made from the flash memory area or the RAM area overlapping flash memory Emulation can be performed in user mode and user program mode Figure 22 16 shows an example of emulation of real time flash memory programming Start emulation program End of emulation program Tuning OK Yes No Set RAMER Write tuning data to overlap RAM Execute application program Write to flash memory emulation ...

Page 761: ...nfirmed the RAMS bit is cleared releasing RAM overlap 4 The data written in the overlapping RAM is written into the flash memory space EB8 Notes 1 When the RAMS bit is set to 1 program erase protection is enabled for all blocks regardless of the value of RAM1 and RAM0 emulation protection In this state setting the P1 or E1 bit in flash memory control register 1 FLMCR1 or the P2 or E2 bit in flash ...

Page 762: ...ure is used and in status read mode detailed internal signals are output after execution of an auto program or auto erase operation In programmer mode set the mode pins to PLL x2 mode see table 22 10 and use a 6 MHz input clock The LSI will then operate at 12 MHz Table 22 10 shows the pin settings for programmer mode For the pin names in programmer mode see section 1 3 2 Pin Arrangement by Mode Ta...

Page 763: ... 20 This will enable conversion to a 32 pin arrangement The on chip ROM memory map is shown in figure 22 18 and socket adapter pin correspondence diagrams in figures 22 19 and 22 20 H 00000000 Addresses in MCU mode Addresses in writer mode H 0003FFFF H 00000 H 3FFFF On chip ROM space 256 kB Figure 22 18 On Chip ROM Memory Map ...

Page 764: ...E I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE VCC VSS A17 Pin Name FWE A9 A16 A15 WE D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE VSS A17 RES XTAL EXTAL PLLVCC PLLCAP PLLVSS NC OPEN HD64F7044 112 Pin Socket Adapter Conversion to 32 Pin Arrangement Power on reset circuit Oscillator circuit PLL circuit Legend FWE Flash ...

Page 765: ...A16 A15 WE I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE VCC VSS A17 Pin Name FWE A9 A16 A15 WE D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE VSS A17 RES XTAL EXTAL PLLVCC PLLCAP PLLVSS NC OPEN HD64F7045 144 Pin Socket Adapter Conversion to 32 Pin Arrangement Power on reset circuit Oscillator circuit PLL circuit Legend F...

Page 766: ... the end of auto programming Status Read Mode Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the I O6 signal In status read mode error information is output if an error occurs Table 22 11 Settings for Various Operating Modes In Programmer Mode Pin names Mode FWE CE OE WE I O7 0 A17 0 Read H or L L L H Data output Ain Output disable H...

Page 767: ...ram mode 129 cycles are required for command writing by a simultaneous 128 byte write 2 In memory read mode the number of cycles depends on the number of address write cycles n 22 11 3 Memory Read Mode Table 22 13 AC Characteristics in Transition to Memory Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 µs CE hold time tceh 0 ns CE ...

Page 768: ...r Memory Read after Memory Write Table 22 14 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns ...

Page 769: ...mode Figure 22 22 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 22 15 AC Characteristics in Memory Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Access time tacc 20 µs CE output delay time tce 150 ns OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns ...

Page 770: ...oh toh Address stable Address stable Figure 22 23 CE and OE Enable State Read Timing Waveforms CE A16 0 OE WE I O7 0 VIH tacc tce toe toe tce tacc toh tdf tdf toh Address stable Address stable Figure 22 24 CE and OE Clock System Read Timing Waveforms ...

Page 771: ...y address transfer is performed in the second cycle figure 22 24 Do not perform transfer after the second cycle 5 Do not perform a command write during a programming operation 6 Perform one auto program operation for a 128 byte block for each address Characteristics are not guaranteed for two or more additional programming operations 7 Confirm normal end of auto programming by checking I O6 Altern...

Page 772: ...ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms Write setup time tpns 100 ns Write end setup time tpnh 100 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A16 0 FWE OE WE I O7 I O6 I O5 0 tpns twep tds tdh tf tr tas tah twsts twrite tspa tces tceh tnxtc tnxtc tpnh Address stable H 40 H 00 Data transfer 1 to 128b...

Page 773: ... write As long as the next command write has not been performed reading is possible by enabling CE and OE Table 22 17 AC Characteristics in Auto Erase Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns Status pol...

Page 774: ...atus Read Mode Table 22 18 AC Characteristics in Status Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Read time after command write tstd 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns OE output delay time toe 150 ns Disable delay time tdf 100 ns CE output delay time tce 150 ...

Page 775: ...error Erase error Program ming or erase count exceeded Effective address error Initial value 0 0 0 0 0 0 0 0 Indications Normal end 0 Abnormal end 1 Command Error 1 Otherwise 0 Program ming Error 1 Otherwise 0 Erasing Error 1 Otherwise 0 Count exceeded 1 Otherwise 0 Effective address Error 1 Otherwise 0 Note D2 and D3 are undefined at present 22 11 7 Status Polling 1 I O7 status polling is a flag ...

Page 776: ...ad mode Table 22 21 Stipulated Transition Times to Command Wait State Item Symbol Min Max Unit Notes Standby release oscillation stabilization time tOSC1 10 ms Programmer mode setup time tbmv 10 ms VCC hold time tdwn 0 ms tOSC1 tbmv tdwn VCC RES FWE Memory read mode Command wait state Automatic write mode Automatic erase mode Command wait state Normal abnormal complete verify Note For the level of...

Page 777: ...uto erasing is recommended before carrying out auto programming Notes 1 The flash memory is initially in the erased state when the device is shipped by Renesas Technology For other chips for which the erasure history is unknown it is recommended that auto erasing be executed to check and supplement the initialization erase level 2 Auto programming should be performed once only on the same address ...

Page 778: ...740 ...

Page 779: ...rea or data area which require high speed access The contents of the on chip RAM are held in both the sleep and standby modes Memory area 0 addresses H FFFFF000 H FFFFFFFF are allocated to the on chip RAM H FFFFF000 H FFFFF004 H FFFFF001 H FFFFF005 H FFFFF002 H FFFFF006 H FFFFF003 H FFFFF007 H FFFFFFFC H FFFFFFFD H FFFFFFFE H FFFFFFFF On chip RAM Internal data bus 32 bits Figure 23 1 Block Diagram...

Page 780: ...742 ...

Page 781: ...instruction with SBY bit set to 0 in SBYCR Run Halt Run Held Held Held Interrupt DMAC DTC address error Power on reset Manual reset Stand by Execute SLEEP instruction with SBY bit set to 1 in SBYCR Halt Halt Halt 1 Held Held Held or high impe dance 2 NMI interrupt Power on reset Manual reset Notes SBYCR standby control register SBY standby bit 1 Some bits within on chip peripheral module registers...

Page 782: ... WDT timer control status register TCSR is set to 1 To enter the standby mode always halt the WDT by 0 clearing the TME bit then set the SBY bit Bit 7 SBY Description 0 Executing SLEEP instruction puts the LSI into sleep mode initial value 1 Executing SLEEP instruction puts the LSI into standby mode Bit 6 Port High Impedance HIZ In the standby mode this bit selects whether to set the I O port pin ...

Page 783: ... If a DMAC DTC address error occurs the sleep mode is canceled and DMAC DTC address error exception processing is executed Cancellation by a Power On Reset A power on reset resulting from setting the RES pin to low level cancels the sleep mode Cancellation by a Manual Reset When the MRES pin is set to low level while the RES pin is at high level a manual reset occurs and the sleep mode is canceled...

Page 784: ...on register DMAOR DMA source address registers 0 3 SAR0 SAR3 DMA destination address registers 0 3 DAR0 DAR3 DMA transfer count registers 0 3 DMATCR0 DMATCR3 Multifunction timer pulse unit MTU MTU associated registers POE associated registers Watchdog timer WDT Bits 7 5 OVF WT IT TME of the timer control status register TCSR Reset control status register RSTCSR Bits 2 0 CKS2 CKS0 of the TCSR Timer...

Page 785: ...ence of this overflow is used to indicate that the clock has stabilized so the clock is supplied to the entire chip the standby mode is canceled and NMI exception processing begins When canceling standby mode with NMI interrupts set the CKS2 CKS0 bits so that the WDT overflow period is longer than the oscillation stabilization time When canceling standby mode with an NMI pin set for falling edge b...

Page 786: ...MI interrupt is accepted When the NMIE bit is set to 1 rising edge detection by an NMI exception service routine the standby bit SBY of the SBYCR is set to 1 and a SLEEP instruction is executed standby mode is entered Thereafter standby mode is canceled when the NMI pin is changed from low to high level Oscillator CK NMI NMIE SBY NMI exception processing Exception service routine SBY 1 SLEEP instr...

Page 787: ...voltage A D ports Vin 0 3 to AVCC 0 3 V Analog supply voltage AVCC 0 3 to 7 0 V Analog reference voltage QFP 144 only AVref 0 3 to AVCC 0 3 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr 20 to 75 1 C Programming temperature ZTAT version only Twe 20 to 75 2 C Storage temperature Tstg 55 to 125 C Notes Operating the LSI in excess of the absolute maximum ratings may result in...

Page 788: ... input pins 2 2 VCC 0 3 V Input low level voltage RES NMI MD3 MD0 PA2 PA5 PA6 PA9 PE0 PE15 FWP VIL 0 3 0 5 V Other input pins 0 3 0 8 V Schmitt trigger input voltage PA2 PA5 PA6 PA9 PE0 PE15 VT VT 0 4 V VT VCC 0 7 V min VT 0 5 V max Input leak current RES NMI MD3 MD0 PA2 PA5 PA6 PA9 PE0 PE15 FWP Iin 1 0 µA Vin 0 5 to VCC 0 5 V A D port 1 0 µA Vin 0 5 to AVCC 0 5 V Other input pins except EXTAL pin...

Page 789: ...ease the AVCC AVSS and AVref SH7041 SH7043 SH7045 only pins Connect the AVCC and AVref SH7041 SH7043 SH7045 only pins to VCC and the AVSS pin to VSS 2 The current consumption is measured when VIHmin VCC 0 5 V VIL max 0 5 V with all output pins unloaded 3 The ZTAT and mask versions as well as F ZTAT and mask versions have the same functions and the electrical characteristics of both are within spec...

Page 790: ... simultaneously 25 3 AC Characteristics 25 3 1 Clock Timing Table 25 4 Clock Timing Conditions VCC 5 0 V 10 AVCC 5 0 V 10 AVCC VCC 10 AVref 4 5 V to AVCC VSS AVSS 0 V Ta 20 to 75 C Item Symbol Min Max Unit Figures Operating frequency fOP 4 28 7 MHz 25 1 Clock cycle time tcyc 34 8 250 ns Clock low level pulse width tCL 10 ns Clock high level pulse width tCH 10 ns Clock rise time tCR 5 ns Clock fall...

Page 791: ...C 1 2VCC tCF tCR CK Figure 25 1 System Clock Timing tEXcyc tEXL tEXH VIH VIH 1 2VCC VIL VIL 1 2VCC tEXF tEXR EXTAL VIH Figure 25 2 EXTAL Clock Input Timing tOSC1 VCC min tOSC2 CK VCC RES Figure 25 3 Oscillation Settling Time ...

Page 792: ...RQES 35 ns IRQ7 IRQ0 setup time level detection tIRQLS 35 ns NMI hold time tNMIH 35 ns 25 5 IRQ7 IRQ0 hold time tIRQEH 35 ns IRQOUT output delay time tIRQOD 35 ns 25 6 Bus request setup time tBRQS 35 ns 25 7 Bus acknowledge delay time 1 tBACKD1 35 ns Bus acknowledge delay time 2 tBACKD2 35 ns Bus three state delay time tBZD 35 ns Note The RES MRES NMI BREQ and IRQ7 IRQ0 signals are asynchronous in...

Page 793: ...W tMRESW tRESr tRESS tMRESS tMRESS tRESS VIH VIH VIH VIL VIL VIL VIL Figure 25 4 Reset Input Timing tNMIH tNMIS tNMIr tNMIf VIH VIL tIRQEH tIRQES VIH VIL tIRQLS CK NMI IRQ edge IRQ level Figure 25 5 Interrupt Signal Input Timing ...

Page 794: ...upt Signal Output Timing CK RD RDWR RAS CASxx CSn WRxx A21 A0 D31 D0 tBRQS tBRQS tBACKD1 tBACKD2 tBZD tBZD BREQ Input Note During the bus release period of a self refresh RAS CASx and RDWR are output BACK Output Figure 25 7 Bus Right Release Timing ...

Page 795: ...lay time 2 tWSD2 2 3 18 ns Write data delay time tWDD 35 ns Write data hold time tWDH 0 10 2 ns WAIT setup time tWTS 15 ns 25 10 25 15 WAIT hold time tWTH 0 ns 25 19 RAS delay time 1 tRASD1 2 3 18 ns 25 11 25 18 RAS delay time 2 tRASD2 2 3 18 ns CAS delay time 1 tCASD1 2 3 18 ns CAS delay time 2 tCASD2 2 3 18 ns Read data access time tACC 1 tcyc n 2 40 ns 25 8 25 9 Access time from read strobe tOE...

Page 796: ...tcyc TPC 1 5 15 ns 25 11 25 16 CAS setup time tCSR 10 ns 25 17 25 18 AH delay time 1 tAHD1 2 3 18 ns 25 19 AH delay time 2 tAHD2 2 3 18 ns Multiplex address delay time tMAD 2 3 18 ns Multiplex address hold time tMAH 0 ns DACK delay time tDACKD1 2 3 21 ns 25 8 25 9 25 11 25 16 25 19 Notes n is the number of waits m is 0 when the number of DRAM write cycle waits is 0 and 1 otherwise RCD is the set v...

Page 797: ... tWSD1 tWSD2 tACC tRDS tRDH tRSD1 tOE tRSD2 tCSD2 tCSD1 tAD tAS tWR tWRH CSn Note tRDH is specified from fastest negate timing of A21 A0 CSn and RD During read During read RD D31 D0 D31 D0 WRxx During write During write Figure 25 8 Basic Cycle No Waits ...

Page 798: ... tDACKD1 tRSD2 tCSD2 tRDS tRDH tWSD2 tWDH tDACKD1 tOE tACC tAS tWRH tWR Note tRDH is specified from fastest negate timing of A21 A0 CSn and RD CSn RD D31 D0 D31 D0 During read During read During write During write WRxx Figure 25 9 Basic Cycle Software Waits ...

Page 799: ...761 CK A21 A0 T1 Tw Two Tw T2 tWTS tWTH tWTS tWTH CSn RD WRxx WAIT DACKn During read During read During write During write D31 D0 D31 D0 Figure 25 10 Basic Cycle 2 Software Waits Wait due to WAIT Signal ...

Page 800: ...CKD1 tRSD1 tRSD2 tWSD1 tWSD2 CK A21 A0 RAS CASxx RDWR D31 D0 D31 D0 CASxx RDWR DACKn RD WRxx Note tRDH is specified from fastest negate timing of A21 A0 RAS and CAS During read During read During read During read During write During write During write During write Row address Column address Figure 25 11 DRAM Cycle Normal Mode No Waits TPC 0 RCD 0 ...

Page 801: ...ACKD1 tRSD1 tWSD1 tWSD2 tRSD2 tCASD1 tRWD1 Row address Column address RAS CASxx RDWR D31 D0 CASxx RDWR D31 D0 DACKn RD WRxx Note tRDH is specified from fastest negate timing of A21 A0 RAS and CAS During read During read During read During read During write During write During write During write Figure 25 12 DRAM Cycle Normal Mode 1 Wait TPC 0 RCD 0 ...

Page 802: ... fastest negate timing of A21 A0 RAS and CAS Figure 25 13 DRAM Cycle Normal Mode 2 Waits TPC 1 RCD 1 CK A21 A0 Tp Tpw Tr Trw Tc1 Tcw1 Tcw2 Tcw3 Tc2 tAD tAD tRAH tASR tRP tCASD1 tCAC tAA tCASD1 tRDS tCASD2 tRWD2 tRWD1 tDS tDH tWDH tDACKD1 tRSD1 tWSD1 tWSD2 tRSD2 tDACKD1 tRASD2 tCASD2 tWDD RAS CASxx RDWR D31 D0 CASxx RDWR D31 D0 DACKn RD WRxx During read During read During read During read During wr...

Page 803: ...SD2 tWSD2 tWSD1 tRSD1 tRASD2 tDACKD1 tCASD2 tRDS RAS CASxx RDWR D31 D0 CASxx RDWR D31 D0 DACKn RD WRxx WAIT During read During read During read During read During write During write During write During write Row address Column address Note tRDH is specified from fastest negate timing of A21 A0 RAS and CAS Figure 25 15 DRAM Cycle Normal Mode 2 Waits Wait due to WAIT Signal ...

Page 804: ...tWSD1 tWSD2 tRSD2 tRSD1 tRSD2 tDACKD1 RAS CASxx RDWR D31 D0 CASxx RDWR D31 D0 DACKn RD WRxx During read During read During read During read During write During write During write During write Note tRDH is specified from fastest negate timing of A21 A0 RAS and CAS Row address Column address Column address Figure 25 16 DRAM Cycle High Speed Page Mode CK RDWR TRp TRr1 TRr2 TRc TRc tRASD1 tRASD2 tCASD...

Page 805: ...D1 tAHD2 tRSD2 tMAH tMAD tRDS tRDH tMAH tWDD tMAD tWDH tDACKD1 tDACKD1 tWTS tWTH tWTS tWTH tWSD2 tWR tWRH tRSD1 CS3 AH D15 D0 WAIT D15 D0 RD WRxx During read Address Address During read During write During write tWSD1 Note tRDH is specified from fastest negate timing of A21 A0 CS3 and RD Figure 25 19 Address Data Multiplex I O Space Cycle 1 Software Wait External Wait ...

Page 806: ...AVCC VSS AVSS 0 V Ta 20 to 75 C Item Symbol Min Max Unit Figure DREQ0 and DREQ1 setup time tDRQS 18 ns 25 20 DREQ0 and DREQ1 hold time tDRQH 18 ns DREQ0 and DREQ1 pulse width tDRQW 1 5 tcyc 25 21 DRAK output delay time tDRAKD 18 ns 25 22 CK tDRQS tDRQS tDRQS tDRQH DREQ0 DREQ1 Level clear DREQ0 DREQ1 Level DREQ0 DREQ1 Edge Figure 25 20 DREQ0 and DREQ1 Input Timing 1 ...

Page 807: ...769 CK tDRQW DREQ0 DREQ1 Edge Figure 25 21 DREQ0 and DREQ1 Input Timing 2 CK tDRAKD tDRAKD DRAKn Figure 25 22 DRAK Output Delay Time ...

Page 808: ...TOCD 100 ns 25 23 Input capture input setup time tTICS 30 ns Timer input setup time tTCKS 35 ns Timer clock pulse width single edge specification tTCKWH L 1 5 tcyc 25 24 Timer clock pulse width both edges specified tTCKWH L 2 5 tcyc Timer clock pulse width phase measurement mode tTCKWH L 2 5 tcyc CK tTOCD tTICS Input capture input Output compare output Figure 25 23 MTU I O Timing CK TCLKA to TCLKD...

Page 809: ... 0 V 10 AVCC VCC 10 AVref 4 5 V to AVCC VSS AVSS 0 V Ta 20 to 75 C Item Symbol Min Max Unit Figure Port output data delay time tPWD 100 ns 25 25 Port input hold time tPRH 35 ns Port input setup time tPRS 35 ns tPRS tPRH tPWD T1 T2 CK Port Read Port Write Figure 25 25 I O Port I O Timing ...

Page 810: ... Watchdog Timer Timing Conditions VCC 5 0 V 10 AVCC 5 0 V 10 AVCC VCC 10 AVref 4 5 V to AVCC VSS AVSS 0 V Ta 20 to 75 C Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD 100 ns 25 26 CK tWOVD WDTOVF tWOVD Figure 25 26 Watchdog Timer Timing ...

Page 811: ...cle clock sync tscyc 6 tcyc Input clock pulse width tsckw 0 4 0 6 tscyc Input clock rise time tsckr 1 5 tcyc Input clock fall time tsckf 1 5 tcyc Transmit data delay time clock sync tTXD 100 ns 25 28 Receive data setup time clock sync tRXS 100 ns Receive data hold time clock sync tRXH 100 ns tsckw tsckr tsckf tscyc SCK0 SCK1 Figure 25 27 Input Clock Timing tscyc tTXD tRXS tRXH SCK0 SCK1 TXD0 TXD1 ...

Page 812: ...Typ Max Unit Figure External trigger input pulse width tTRGW 2 tcyc 25 29 External trigger input start delay time tTRGS 50 ns A D conversion start delay time CKS 0 tD 1 5 1 5 1 5 tcyc 25 30 CKS 1 1 5 1 5 1 5 Input sampling time CKS 0 tSPL 20 20 20 CKS 1 40 40 40 A D conversion time CKS 0 tCONV 42 5 42 5 42 5 CKS 1 82 5 82 5 82 5 tTRGS CK ADCR tTRGW tTRGW ADTRG input 1 state Figure 25 29 External T...

Page 813: ...DF tD tD tSPL tCONV tCP tSPL tCP tCONV ADST A D conversion start delay time Input sampling time A D conversion time Operation time Address Write signal Sampling timing φ Figure 25 30 Analog Conversion Timing ...

Page 814: ... Ta 20 to 75 C Item Symbol Min Typ Max Unit Figure External trigger input pulse width tTRGW 2 tcyc 25 31 External trigger input start delay time tTRGS 50 ns A D conversion start delay time CKS 0 tD 10 17 tcyc 25 32 CKS 1 6 9 Input sampling time CKS 0 tSPL 64 CKS 1 32 A D conversion time CKS 0 tCONV 259 266 CKS 1 131 134 tTRGS CK ADCR ADTRG input tTRGW tTRGW 1 state Figure 25 31 External Trigger In...

Page 815: ...ONV tD tSPL tCONV ADCSR write cycle ADCSR address A D conversion start delay time Input sampling time A D conversion time Address Write signal Input sampling timing CK 1 2 Legend 1 2 Figure 25 32 Analog Conversion Timing ...

Page 816: ... LSI output pin DUT output CL is set with the following pins including the total capacitance of the measurement equipment etc Note 30 pF 50 pF 70 pF IOL IOH CK RAS CASxx RDWR CS0 CS3 AH BREQ BACK DACK0 DACK1 and IRQOUT A21 A0 D31 D0 RD WRxx Port output and peripheral module output pins other than the above See table 25 3 Permitted Output Current Values Figure 25 33 Output Load Circuit ...

Page 817: ... 8 LSB Full scale error 8 LSB Quantization error 0 5 LSB Absolute error when CKS 1 15 LSB Note Reference values Table 25 16 A D Converter Timing A mask Condition Vcc 5 0 10 AVcc 5 0 10 AVcc Vcc 10 AVref 4 5V to AVcc Vss AVss 0V Ta 20 to 75 C 28 7 MHz 20 MHz Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 Bits Conversion time when CKS 0 9 3 13 4 µs Analog input capacity 20 20 pF Perm...

Page 818: ...780 ...

Page 819: ...e other than A D ports Vin 0 3 to VCC 0 3 V Input voltage A D ports Vin 0 3 to AVCC 0 3 V Analog supply voltage AVCC 0 3 to 7 0 V Analog reference voltage QFP 144 only AVref 0 3 to AVCC 0 3 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr 20 to 75 C Programming temperature ZTAT version only Twe 20 to 75 C Storage temperature Tstg 55 to 125 C Note Operating the LSI in excess ...

Page 820: ... input pins VCC 0 7 VCC 0 3 V Input low level voltage RES NMI MD3 0 PA2 PA5 PA6 PA9 PA0 PE15 FWP VIL 0 3 VCC 0 1 V Other input pins 0 3 VCC 0 2 V Schmitt trigger input voltage PA2 PA5 PA6 PA9 PE0 PE15 VT VT VCC 0 07 V VT VCC 0 9V min VT VCC 0 2V max Input leak current RES NMI MD3 0 PA2 PA5 PA6 PA9 PE0 PE15 FWP lin 1 0 µA Vin 0 5 to VCC 0 5V A D port 1 0 µA Vin 0 5 to AVCC 0 5V Other input pins exc...

Page 821: ...P144 version only RAM standby voltage VRAM 2 0 V Notes 1 Do not release AVCC AVSS and AVref SH7041 SH7043 and SH7045 only pins when not using the A D converter including standby Connect AVCC SH7041 SH7043 SH7045 only and AVref SH7041 SH7043 and SH7045 only pins to VCC and AVSS pin to VSS 2 The value for consumed current is with conditions of VIHmin VCC 0 5V and VILmax 0 5V with no burden on any of...

Page 822: ...able 26 4 Clock Timing Conditions VCC 3 0 to 3 6V AVCC 3 0 to 3 6V AVCC VCC 10 AVref 3 0 to AVCC VSS AVSS 0V Ta 20 to 75 C Item Symbol Min Max Unit Figures Operating frequency fOP 4 16 7 MHz 26 1 Clock cycle time tcyc 60 250 ns Clock low level pulse width tCL 10 ns Clock high level pulse width tCH 10 ns Clock rise time tCR 5 ns Clock fall time tCF 5 ns EXTAL clock input frequency fEX 4 10 MHz 26 2...

Page 823: ...C 1 2VCC tCF tCR CK Figure 26 1 System Clock Timing tEXcyc tEXL tEXH VIH VIH 1 2VCC VIL VIL 1 2VCC tEXF tEXR EXTAL VIH Figure 26 2 EXTAL Clock Input Timing tOSC1 VCC min tOSC2 CK VCC RES Figure 26 3 Oscillation Settling Time ...

Page 824: ...100 ns IRQ7 IRQ0 setup time level detection 2 tIRQLS 100 ns NMI hold time tNMIH 50 ns 26 5 IRQ7 IRQ0 hold time tIRQEH 50 ns IRQOUT output delay time tIRQOD 50 ns 26 6 Bus request setup time tBRQS 35 ns 26 7 Bus acknowledge delay time 1 tBACKD1 35 ns Bus acknowledge delay time 2 tBACKD2 35 ns Bus three state delay time tBZD 35 ns Notes 1 SH7042 43 ZTAT excluding A mask are 3 2V 2 The RES MRES NMI B...

Page 825: ...W tMRESW tRESr tRESS tMRESS tMRESS tRESS VIH VIH VIH VIL VIL VIL VIL Figure 26 4 Reset Input Timing tNMIH tNMIS tNMIr tNMIf VIH VIL tIRQEH tIRQES VIH VIL tIRQLS CK NMI IRQ edge IRQ level Figure 26 5 Interrupt Signal Input Timing ...

Page 826: ...upt Signal Output Timing CK RD RDWR RAS CASxx CSn WRxx A21 A0 D31 D0 tBRQS tBRQS tBACKD1 tBACKD2 tBZD tBZD BREQ Input Note During the bus release period of a self refresh RAS CASx and RDWR are output BACK Output Figure 26 7 Bus Right Release Timing ...

Page 827: ... 1 tRASD1 3 4 35 ns 26 11 18 RAS delay time 2 tRASD2 3 4 35 ns CAS delay time 1 tCASD1 3 4 35 ns CAS delay time 2 tCASD2 3 4 35 ns Read data access time tACC 2 tcyc n 2 45 ns 26 8 9 Access time from read strobe tOE 2 tcyc n 1 5 40 ns Access time from column address tAA 2 tcyc n 2 45 ns 26 11 16 Access time from RAS tRAC 2 tcyc n RCD 2 5 40 ns Access time from CAS tCAC 2 tcyc n 1 40 ns Row address ...

Page 828: ...1 16 Read write strobe delay time 2 tRWD2 3 2 27 ns High speed page mode CAS tCP tcyc 35 ns 26 16 RAS precharge time tRP tcyc TPC 1 5 20 ns 26 11 16 CAS setup time tCSR 10 ns 26 17 18 AH delay time 1 tAHD1 3 2 40 ns 26 19 AH delay time 2 tAHD2 3 2 40 ns Multiplex address delay time tMAD 3 2 35 ns Multiplex address hold time tMAH 0 ns DACK delay time 1 tDACKD1 3 2 45 ns 26 8 9 11 16 19 Notes TPC is...

Page 829: ... tWSD1 tWSD2 tACC tRDS tRDH tRSD1 tOE tRSD2 tCSD2 tCSD1 tAD tAS tWR tWRH CSn Note tRDH is specified from fastest negate timing of A21 A0 CSn and RD During read During read RD D31 D0 D31 D0 WRxx During write During write Figure 26 8 Basic Cycle No Waits ...

Page 830: ... tDACKD1 tRSD2 tCSD2 tRDS tRDH tWSD2 tWDH tDACKD1 tOE tACC tAS tWRH tWR Note tRDH is specified from fastest negate timing of A21 A0 CSn and RD CSn RD D31 D0 D31 D0 During read During read During write During write WRxx Figure 26 9 Basic Cycle Software Waits ...

Page 831: ...793 CK A21 A0 T1 Tw Two Tw T2 tWTS tWTH tWTS tWTH CSn RD WRxx WAIT DACKn During read During read During write During write D31 D0 D31 D0 Figure 26 10 Basic Cycle 2 Software Waits Wait due to WAIT Signal ...

Page 832: ...ACKD1 tRSD1 tRSD2 tWSD1 tWSD2 CK A21 A0 RAS CASxx RDWR D31 D0 D31 D0 CASxx RDWR DACKn RD WRxx Note tRDH is specified from fastest negate timing of A21 A0 RAS and CAS During read During read During read During read During write During write During write During write Row address Column address Figure 26 11 DRAM Cycle Normal Mode No Wait TPC 0 RCD 0 ...

Page 833: ...ACKD1 tRSD1 tWSD1 tWSD2 tRSD2 tCASD1 tRWD1 Row address Column address RAS CASxx RDWR D31 D0 CASxx RDWR D31 D0 DACKn RD WRxx Note tRDH is specified from fastest negate timing of A21 A0 RAS and CAS During read During read During read During read During write During write During write During write Figure 26 12 DRAM Cycle Normal Mode 1 Wait TPC 0 RCD 0 ...

Page 834: ... fastest negate timing of A21 A0 RAS and CAS Figure 26 13 DRAM Cycle Normal Mode 2 Waits TPC 1 RCD 1 CK A21 A0 Tp Tpw Tr Trw Tc1 Tcw1 Tcw2 Tcw3 Tc2 tAD tAD tRAH tASR tRP tCASD1 tCAC tAA tCASD1 tRDS tCASD2 tRWD2 tRWD1 tDS tDH tWDH tDACKD1 tRSD1 tWSD1 tWSD2 tRSD2 tDACKD1 tRASD2 tCASD2 tWDD RAS CASxx RDWR D31 D0 CASxx RDWR D31 D0 DACKn RD WRxx During read During read During read During read During wr...

Page 835: ...SD2 tWSD2 tWSD1 tRSD1 tRASD2 tDACKD1 tCASD2 tRDS RAS CASxx RDWR D31 D0 CASxx RDWR D31 D0 DACKn RD WRxx WAIT During read During read During read During read During write During write During write During write Row address Column address Note tRDH is specified from fastest negate timing of A21 A0 RAS and CAS Figure 26 15 DRAM Cycle Normal Mode 2 Waits Wait due to WAIT Signal ...

Page 836: ...tWSD1 tWSD2 tRSD2 tRSD1 tRSD2 tDACKD1 RAS CASxx RDWR D31 D0 CASxx RDWR D31 D0 DACKn RD WRxx During read During read During read During read During write During write During write During write Note tRDH is specified from fastest negate timing of A21 A0 RAS and CAS Row address Column address Column address Figure 26 16 DRAM Cycle High Speed Page Mode CK RDWR TRp TRr1 TRr2 TRc TRc tRASD1 tRASD2 tCASD...

Page 837: ...D1 tAHD2 tRSD2 tMAH tMAD tRDS tRDH tMAH tWDD tMAD tWDH tDACKD1 tDACKD1 tWTS tWTH tWTS tWTH tWSD2 tRSD1 CS3 AH D15 D0 WAIT D15 D0 RD WRxx During read Address Address During read During write During write tWSD1 Note tRDH is specified from fastest negate timing of A21 A0 CS3 and RD tWR tWRH Figure 26 19 Address Data Multiplex I O Space Cycle 1 Software Wait External Wait ...

Page 838: ...V Ta 20 to 75 C Item Symbol Min Max Unit Figure DREQ0 DREQ1 setup time tDRQS 35 ns 26 20 DREQ0 DREQ1 hold time tDRQH 35 ns DREQ0 DREQ1 pulse width tDRQW 1 5 tcyc 26 21 DRAK output delay time tDRAKD 35 ns 26 22 Note SH7042 43 ZTAT excluding A mask are 3 2V CK tDRQS tDRQS tDRQS tDRQH DREQ0 DREQ1 Level clear DREQ0 DREQ1 Level DREQ0 DREQ1 Edge Figure 26 20 DREQ0 and DREQ1 Input Timing 1 ...

Page 839: ...801 CK tDRQW DREQ0 DREQ1 Edge Figure 26 21 DREQ0 and DREQ1 Input Timing 2 CK tDRAKD tDRAKD DRAKn Figure 26 22 DRAK Output Delay Time ...

Page 840: ...t capture input setup time tTICS 100 ns Timer input setup time tTCKS 100 ns 26 24 Timer clock pulse width single edge specification tTCKWH L 1 5 tcyc Timer clock pulse width both edges specified tTCKWH L 2 5 tcyc Timer clock pulse width phase measurement mode tTCKWH L 2 5 tcyc Note SH7042 43 ZTAT excluding A mask are 3 2V CK tTOCD tTICS Input capture input Output compare output Figure 26 23 MTU I ...

Page 841: ...AVref 3 0 to AVCC VSS AVSS 0V Ta 20 to 75 C Item Symbol Min Max Unit Figure Port output data delay time tPWD 100 ns 26 25 Port input hold time tPRH 100 ns Port input setup time tPRS 100 ns Note SH7042 43 ZTAT excluding A mask are 3 2V tPRS tPRH tPWD T1 T2 CK Port Read Port Write Figure 26 25 I O Port I O Timing ...

Page 842: ...onditions VCC 3 0 to 3 6V AVCC 3 0 to 3 6V AVCC VCC 10 AVref 3 0 to AVCC VSS AVSS 0V Ta 20 to 75 C Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD 100 ns 26 26 Note SH7042 43 ZTAT excluding A mask are 3 2V CK tWOVD WDTOVF tWOVD Figure 26 26 Watchdog Timer Timing ...

Page 843: ...6 tcyc Input clock pulse width tsckw 0 5 0 6 tscyc Input clock rise time tsckr 1 5 tcyc Input clock fall time tsckf 1 5 tcyc Transmit data delay time clock sync tTXD 100 ns 26 28 Receive data setup time clock sync tRXS 100 ns Receive data hold time clock sync tRXH 100 ns Note SH7042 43 ZTAT excluding A mask are 3 2V tsckw tsckr tsckf tscyc SCK0 SCK1 Figure 26 27 Input Clock Timing tscyc tTXD tRXS ...

Page 844: ...ternal trigger input pulse width tTRGW 2 tcyc 26 29 External trigger input start delay time tTRGS 50 ns A D conversion start delay time CKS 0 tD 1 5 1 5 1 5 tcyc 26 30 CKS 1 1 5 1 5 1 5 Input sampling time CKS 0 tSPL 20 20 20 CKS 1 40 40 40 A D conversion time CKS 0 tCONV 42 5 42 5 42 5 CKS 1 82 5 82 5 82 5 Note SH7042 43 ZTAT excluding A mask are 3 2V tTRGS CK ADST ADTRG input tTRGW tTRGW 1 state...

Page 845: ...DF tD tD tSPL tCONV tCP tSPL tCP tCONV ADST A D conversion start delay time Input sampling time A D conversion time Operation time Address Write signal Sampling timing φ Figure 26 30 Analog Conversion Timing ...

Page 846: ...nit Figure External trigger input pulse width tTRGW 2 tcyc 26 31 External trigger input start delay time tTRGS 50 ns A D conversion start delay time CKS 0 tD 10 17 tcyc 26 32 CKS 1 6 9 Input sampling time CKS 0 tSPL 64 CKS 1 32 A D conversion time CKS 0 tCONV 259 266 CKS 1 131 134 Note SH7042 43 ZTAT excluding A mask are 3 2V tTRGS CK ADST tTRGW tTRGW ADTRG input 1 state Figure 26 31 External Trig...

Page 847: ...ONV tD tSPL tCONV ADCSR write cycle ADCSR address A D conversion start delay time Input sampling time A D conversion time Address Write signal Input sampling timing CK 1 2 Legend 1 2 Figure 26 32 Analog Conversion Timing ...

Page 848: ...V LSI output pin DUT output CL is set with the following pins including the total capacitance of the measurement equipment etc Note 30 pF 50 pF 70 pF IOL IOH CK RAS CASxx RDWR CS0 CS3 AH BREQ BACK DACK0 DACK1 and IRQOUT A21 A0 D31 D0 RD WRxx Port output and peripheral module output pins other than the above See table 26 3 Permitted Output Current Values Figure 26 33 Output Load Circuit ...

Page 849: ...r 2 15 LSB Quantize error 2 0 5 LSB Absolute error 31 LSB Notes 1 SH7042 43 ZTAT excluding A mask are 3 2V 2 Reference values Table 26 16 A D Converter Characteristics A mask Conditions VCC 3 0 1 to 3 6V AVCC 3 0 1 to 3 6V AVCC VCC 10 AVref 3 0 1 to AVCC VSS AVSS 0V Ta 20 to 75 C 16 7MHz Item min typ max Unit Resolution 10 10 10 bit Conversion time when CKS 0 16 0 µs Analog input capacity 20 pF Pe...

Page 850: ...812 ...

Page 851: ... Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DTMR SM1 SM0 DM1 DM0 MD1 MD0 SZ1 SZ0 DTC DTS CHNE DISEL NMIM DTSAR DTDAR DTIAR DTCRA DTCRB H FFFF81A0 SMR0 C A CHR PE O E STOP MP CKS1 CKS0 SCI H FFFF81A1 BRR0 H FFFF81A2 SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H FFFF81A3 TDR0 H FFFF81A4 SSR0 TDRE RDRF ORER FER PER TEND MPB MPBT H FFFF81A5 RDR0 H FFFF81A6 to H FFFF81AF ...

Page 852: ... FFFF8202 TMDR3 BFB BFA MD3 MD2 MD1 MD0 H FFFF8203 TMDR4 BFB BFA MD3 MD2 MD1 MD0 H FFFF8204 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FFFF8205 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H FFFF8206 TIOR4H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FFFF8207 TIOR4L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H FFFF8208 TIER3 TTGE TCIEV TGIED TGIEC TGIEB TGIEA H FFFF8209 TIER4 TTGE TCIEV TGIED T...

Page 853: ... H FFFF822C TSR3 TCFD TCFV TGFD TGFC TGFB TGFA H FFFF822D TSR4 TCFD TCFV TGFD TGFC TGFB TGFA H FFFF822E H FFFF822F H FFFF8230 to H FFFF823F H FFFF8240 TSTR CST4 CST3 CST2 CST1 CST0 H FFFF8241 TSYR SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 H FFFF8242 to H FFFF825F H FFFF8260 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H FFFF8261 TMDR0 BFB BFA MD3 MD2 MD1 MD0 H FFFF8262 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 ...

Page 854: ...TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FFFF8283 H FFFF8284 TIER1 TTGE TCIEU TCIEV TGIEB TGIEA H FFFF8285 TSR1 TCFD TCFU TCFV TGFB TGFA H FFFF8286 TCNT1 H FFFF8287 H FFFF8288 TGR1A H FFFF8289 H FFFF828A TGR1B H FFFF828B H FFFF828C to H FFFF829F H FFFF82A0 TCR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H FFFF82A1 TMDR2 MD3 MD2 MD1 MD0 H FFFF82A2 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0...

Page 855: ...RQ7S H FFFF835A ISR H FFFF835B IRQ0F IRQ1F IRQ2F IRQ3F IRQ4F IRQ5F IRQ6F IRQ7F H FFFF835C to H FFFF837F H FFFF8380 PADRH I O H FFFF8381 PA23DR PA22DR PA21DR PA20DR PA19DR PA18DR PA17DR PA16DR H FFFF8382 PADRL PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR H FFFF8383 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR H FFFF8384 PAIORH PFC H FFFF8385 PA23IOR PA22IOR PA21IOR PA20IOR PA19IOR PA18I...

Page 856: ... PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 H FFFF839B PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD PB0MD H FFFF839C PCCR PC15MD PC14MD PC13MD PC12MD PC11MD PC10MD PC9MD PC8MD H FFFF839D PC7MD PC6MD PC5MD PC4MD PC3MD PC2MD PC1MD PC0MD H FFFF839E H FFFF839F H FFFF83A0 PDDRH PD31DR PD30DR PD29DR PD28DR PD27DR PD26DR PD25DR PD24DR I O H FFFF83A1 PD23DR PD22DR PD21DR PD20DR PD19DR PD18DR PD17DR PD16DR H FFFF83A2 PDDRL P...

Page 857: ...OR PE11IOR PE10IOR PE9IOR PE8IOR PFC H FFFF83B5 PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR H FFFF83B6 H FFFF83B7 H FFFF83B8 PECR1 PE15MD1 PE15MD0 PE14MD1 PE14MD0 PE13MD1 PE13MD0 PE12MD H FFFF83B9 PE11MD PE10MD PE9MD PE8MD H FFFF83BA PECR2 PE7MD PE6MD PE5MD PE4MD H FFFF83BB PE3MD1 PE3MD0 PE2MD1 PE2MD0 PE1MD1 PE1MD0 PE0MD1 PE0MD0 H FFFF83BC to H FFFF83BF H FFFF83C0 ICSR POE3F POE2F POE1...

Page 858: ...AD1 AD0 H FFFF83F2 ADDRB AD9 AD8 H FFFF83F3 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 H FFFF83F4 ADDRC AD9 AD8 H FFFF83F5 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 H FFFF83F6 ADDRD AD9 AD8 H FFFF83F7 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 H FFFF83F8 ADDRE AD9 AD8 H FFFF83F9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 H FFFF83FA ADDRF AD9 AD8 H FFFF83FB AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 H FFFF83FC ADDRG AD9 AD8 H FFFF83FD AD7 AD6 AD5 AD4 ...

Page 859: ...FF8414 to H FFFF857F H FFFF8580 FLMCR1 FWE SWE ESU1 PSU1 EV1 PV1 E1 P1 FLASH H FFFF8581 FLMCR2 FLER ESU2 PSU2 EV2 PV2 E2 P2 F ZTAT H FFFF8582 EBR1 EB3 EB2 EB1 EB0 version H FFFF8583 EBR2 EB11 EB10 EB9 EB8 EB7 EB6 EB5 EB4 only H FFFF8584 to H FFFF859F H FFFF8600 UBARH UBA31 UBA30 UBA29 UBA28 UBA27 UBA26 UBA25 UBA24 UBC H FFFF8601 UBA23 UBA22 UBA21 UBA20 UBA19 UBA18 UBA17 UBA16 H FFFF8602 UBARL UBA1...

Page 860: ...IW21 IW20 IW11 IW10 IW01 IW00 H FFFF8623 CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0 H FFFF8624 WCR1 W33 W32 W31 W30 W23 W22 W21 W20 H FFFF8625 W13 W12 W11 W10 W03 W02 W01 W00 H FFFF8626 WCR2 H FFFF8627 DDW1 DDW0 DSW3 DSW2 DSW1 DSW0 H FFFF8628 RAMER FLASH F ZTAT H FFFF8629 RAMS RAM1 RAM0 version only H FFFF862A DCR TPC RCD TRAS1 TRAS0 DWW1 DWW0 DWR1 DWR0 BSC H FFFF862B DIW BE RASD SZ1 SZ0 AMX1 AMX0 H FFFF862C...

Page 861: ...o H FFFF86BF H FFFF86C0 SAR0 H FFFF86C1 H FFFF86C2 H FFFF86C3 H FFFF86C4 DAR0 H FFFF86C5 H FFFF86C6 H FFFF86C7 H FFFF86C8 DMATCR0 H FFFF86C9 H FFFF86CA H FFFF86CB H FFFF86CC CHCR0 H FFFF86CD DI RO RL AM AL H FFFF86CE DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H FFFF86CF DS TM TS1 TS0 IE TE DE H FFFF86D0 SAR1 H FFFF86D1 H FFFF86D2 H FFFF86D3 H FFFF86D4 DAR1 H FFFF86D5 H FFFF86D6 H FFFF86D7 H FFFF86D8 DMATCR1 ...

Page 862: ...H FFFF86E3 H FFFF86E4 DAR2 H FFFF86E5 H FFFF86E6 H FFFF86E7 H FFFF86E8 DMATCR2 H FFFF86E9 H FFFF86EA H FFFF86EB H FFFF86EC CHCR2 H FFFF86ED DI RO RL AM AL H FFFF86EE DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H FFFF86EF DS TM TS1 TS0 IE TE DE H FFFF86F0 SAR3 H FFFF86F1 H FFFF86F2 H FFFF86F3 H FFFF86F4 DAR3 H FFFF86F5 H FFFF86F6 H FFFF86F7 H FFFF86F8 DMATCR3 H FFFF86F9 H FFFF86FA H FFFF86FB H FFFF86FC CHCR3 H...

Page 863: ...DTE3 DTE2 DTE1 DTE0 H FFFF8702 DTEC DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 H FFFF8703 DTED DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 H FFFF8704 DTEE DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 H FFFF8705 H FFFF8706 DTCSR NMIF AE SWDTE H FFFF8707 DTVEC7 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 H FFFF8708 DTBR H FFFF8709 H FFFF870A to H FFFF873F H FFFF8740 CCR CAC H FFFF8741 CEDRAM CECS3 CECS2 CE...

Page 864: ... Diagrams PAR Internal data bus RES PFC Standby PAW PAnDR Q R C D Q PAnMD Q PAnIOR SBYCR RXDm Q HIZ SCI n 0 3 m 0 1 PAR Port A read signal PAW Port A write signal RES Reset signal PAn RXDm Figure B 1 PAn RXDm Block Diagram ...

Page 865: ...PFC Standby PAW PAnDR Q C D SBYCR INTC IRQm n 2 5 m 0 1 PAR Port A read signal PAW Port A write signal RES Reset signal DMAC DREQm SCI SCKmIN Q PAnMD0 Q PAnIOR Q HIZ Q PAnMD1 PAn SCKm DREQm IRQm Figure B 2 PAn SCKm DREQm IRQm Block Diagram ...

Page 866: ... Standby PAW PAnDR Q C D Q PAnMD0 Q PAnMD1 Q PAnIOR Q HIZ TCLKA TCLKB SBYCR MTU n 6 7 PAR Port A read signal PAW Port A write signal RES Reset signal R PA6 TCLKA CS2 PA7 TCLKB CS3 Figure B 3 PA6 TCLKA CS2 PA7 TCLKB CS3 ZTAT Mask Block Diagram ...

Page 867: ...Q PA7DR PFC SBYCR WE Q HIZ MTU TCLKB CS3 Q PA7IOR PA7 TCLKB CS3 PAR Port A read signal PAW Port A write signal RES Reset signal On chip flash memory Writer mode Internal data bus Standby Figure B 4 PA7 TCLKB CS3 Block Diagram F ZTAT Version ...

Page 868: ...by PAW PAnDR Q C D TCLKC TLCKD SBYCR MTU n 8 9 PAR Port A read signal PAW Port A write signal RES Reset signal IRQ2 IRQ3 INTC R Q PAnMD0 Q PAnMD1 Q PAnIOR Q HIZ PA8 TCLKC IRQ2 PA9 TCLKD IRQ3 Figure B 5 PAn TCLKm IRQx Block Diagram ZTAT Mask ...

Page 869: ... CE Q HIZ MTU TCLKC D INTC IRQ2 IRQ3 Q PAnIOR PA8 TCLKC IRQ2 PA9 TCLKD IRQ3 n 8 9 PAR Port A read signal PAW Port A write signal RES Reset signal On chip flash memory Writer mode Internal data bus Standby Figure B 6 PAn TCLKm IRQx Block Diagram F ZTAT Version ...

Page 870: ...AR Internal data bus RES TXDm PFC Standby PAW Q PAnMD Q PAnIOR Q HIZ STBCR n 1 4 m 0 1 PAR Port A read signal PAW Port A write signal RES Reset signal PAnDR Q C D R PAn TXDm Figure B 7 PAn TXDm Block Diagram ...

Page 871: ... bus RES CK Single mode MCU mode 2 MCU mode 1 MCU mode 0 PFC Standby PAW STBCR PAR Port A read signal PAW Port A write signal RES Reset signal PA15DR Q C D R PA15 CK Q PA15IOR Q PA15MD Q HIZ Figure B 8 PA15 CK Block Diagram ...

Page 872: ...ta bus RES DRAK0 PFC Standby PAW SBYCR PAR Port A read signal PAW Port A write signal RES Reset signal PA18DR Q C D R BSC BREQ PA18 DRAK0 BREQ Q PA18IMD1 Q PA18IOR Q PA18MD0 Q HIZ Figure B 9 PA18 DRAK0 BREQ Block Diagram ...

Page 873: ...RES DRAK1 BACK PFC Standby Bus right release PAW SBYCR PAR Port A read signal PAW Port A write signal RES Reset signal PA19DR Q C D R Q HIZ PA19 DRAK1 BACK Q PA19MD0 Q PA19MD1 Q PA19IOR Figure B 10 PA19 DRAQ1 BACK Block Diagram ...

Page 874: ... WRH RD Single mode MCU mode 0 MCU mode 1 MCU mode 2 PFC SBYCR Standby Bus right release PAW n 10 14 PAR Port A read signal PAW Port A write signal RES Reset signal PAnDR Q C D R Q PAnMD Q PAnIOR Q HIZ PAn XXX Figure B 11 PAn XXX Block Diagram ...

Page 875: ...AH CASHL CASHH WRHL WRHH Single mode PFC SBYCR Standby Bus right release PAW n 16 20 23 PAR Port A read signal PAW Port A write signal RES Reset signal PAnDR Q C D R Q PAnMD Q HIZ Q PAnIOR PAn XXXX Figure B 12 PAn XXXX Block Diagram ...

Page 876: ... bus RES Single mode PFC SBYCR Standby Bus right release PAW PAR Port A read signal PAW Port A write signal RES Reset signal PAnDR Q C D R Q PA17MD Q HIZ WAIT request Q PA17IOR PA17 WAIT Figure B 13 PA17 WAIT Block Diagram ...

Page 877: ...U mode 1 MCU mode 2 A16 PFC SBYCR Standby Bus right release PBW PBR Port B read signal PBW Port B write signal RES Reset signal PB0DR Q C D R On chip EPROM A16 PB0 A16 Q PB0MD Q PB0IOR Q HIZ Note Not available with the mask versions Figure B 14 PB0 A16 Block Diagram ...

Page 878: ...SBYCR Q HIZ A16 PBR Port B read signal PBW Port B write signal RES Reset signal On chip flash memory Writer mode Internal data bus Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Standby PB0 A16 Figure B 15 PB0 A16 Block Diagram F ZTAT Version ...

Page 879: ...Single mode MCU mode 0 MCU mode 1 MCU mode 2 A17 PFC SBYCR Standby Bus right release PBW PBR Port B read signal PBW Port B write signal RES Reset signal PB1DR Q C D R PB1 A17 Q PB1MD Q PB1IOR Q HIZ Figure B 16 PB1 A17 Block Diagram ...

Page 880: ... A18 BACK PFC SBYCR INTC IRQ4 Standby Bus right release PBW PBR Port B read signal PBW Port B write signal RES Reset signal PB6DR Q C D Q PB6MD0 Q PB6MD1 Q PB6IOR Q HIZ PB6 IRQ4 A18 BACK Figure B 17 PB6 IRQ4 A18 BACK Block Diagram ...

Page 881: ...Bus right release PBW n 3 4 m 1 2 PBR Port B read signal PBW Port B write signal RES Reset signal PBnDR Q C D On chip EPROM OE PGM Q PBnMD0 Q PBnMD1 Q HIZ Q PBnIOR INTC IRQm PBn IRQm POEm CASx Note Not available with the ZTAT version Figure B 18 PBn IRQm POEm CASx Block Diagram ...

Page 882: ...INTC IRQm PB4 IRQ2 POE2 CASH PB3 IRQ1 POE1 CASL n 3 4 m 1 2 PBR Port B read signal PBW Port B write signal RES Reset signal Note Only when n 4 On chip flash memory Internal data bus Writer mode Standby Bus right release Figure B 19 PB4 IRQ2 POE2 CASH PB3 IRQ1 POE1 CASL Block Diagram F ZTAT Version ...

Page 883: ...CR BSC AD BREQ WAIT ADTRG Standby Bus right release PBW n 7 9 m 5 7 PBR Port B read signal PBW Port B write signal RES Reset signal PBnDR Q C D Q PBnMD0 Q PBnMD1 Q HIZ Q PBnIOR INTC IRQm PBn IRQm XXX YYY Figure B 20 PBn IRQm XXX YYY Block Diagram ...

Page 884: ... SBYCR POE POE0 POE3 Standby Bus right release PBW n 2 5 m 0 3 PBR Port B read signal PBW Port B write signal RES Reset signal PBnDR Q C D Q PBnMD0 Q PBnMD1 Q HIZ Q PBnIOR INTC IRQm PBn IRQm XXX YYY Figure B 21 PBn IRQm XXXX YYYY Block Diagram ...

Page 885: ... mode 1 MCU mode 2 An PFC SBYCR Standby Bus right release PCW n 0 15 PCR Port C read signal PCW Port C write signal RES Reset signal PCnDR Q C D R On chip EPROM An Q PBnMD Q PBnIOR Q HIZ PCn An Note Not available with the mask versions Figure B 22 PCn An Block Diagram ...

Page 886: ...CR Q HIZ An PCn An n 0 15 PCR Port C read signal PCW Port C write signal RES Reset signal On chip flash memory Writer mode Internal data bus Single mode Bus right release Standby MCU mode 2 MCU mode 0 MCU mode 1 Figure B 23 PCn An Block Diagram F ZTAT Version ...

Page 887: ...n Standby Bus right release SLEEP PDW n 0 7 PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data output timing signal Din Data bus input timing signal PDnDR Q C D R On chip EPROM Dn Q PDnMD Q PDnIOR Q HIZ PDn Dn Note Not available with the mask version Figure B 24 PDn Dn Block Diagram ...

Page 888: ... Internal data bus PDn Dn Writer mode Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Sleep Standby n 0 15 PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data bus output timing signal Din Data bus input timing signal Figure B 25 PDn Dn Block Diagram F ZTAT Version ...

Page 889: ... mode MCU mode 1 MCU mode 0 MCU mode 2 PFC SBYCR Q HIZ QPDnMD0 QPDnMD1 QPDnIOR INTC IRQm Internal data bus n 16 23 m 0 7 PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data output timing signal Din Data bus input timing signal Figure B 26 PDn Dn IRQm Block Diagram n 16 23 ...

Page 890: ...mode MCU mode 1 MCU mode 0 MCU mode 2 PFC SBYCR Q HIZ QPDnMD0 QPDnMD1 QPDnIOR DMAC DREQm Internal data bus n 24 25 m 0 1 PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data output timing signal Din Data bus input timing signal Figure B 27 PDn Dn DREQm Block Diagram n 24 25 ...

Page 891: ...le mode MCU mode 1 MCU mode 0 MCU mode 2 PFC SBYCR Q HIZ QPDnMD0 QPDnMD1 QPDnIOR Internal data bus n 26 27 m 0 1 PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data output timing signal Din Data bus input timing signal DACKm Figure B 28 PDn Dn DACKm Block Diagram n 26 27 ...

Page 892: ...gle mode MCU mode 1 MCU mode 0 MCU mode 2 PFC SBYCR Q HIZ QPDnMD0 QPDnMD1 QPDnIOR Internal data bus n 28 29 m 2 3 PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data output timing signal Din Data bus input timing signal CSm Figure B 29 PDn Dn CSm Block Diagram n 28 29 ...

Page 893: ... Single mode MCU mode 1 MCU mode 0 MCU mode 2 PFC SBYCR Q HIZ QPDnMD0 QPDnMD1 QPDnIOR Internal data bus n 30 PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data output timing signal Din Data bus input timing signal IRQOUT Figure B 30 PDn Dn IRQOUT Block Diagram n 30 ...

Page 894: ...out Single mode MCU mode 1 MCU mode 0 MCU mode 2 PFC SBYCR Q HIZ QPD31MD0 QPD31MD1 QPD31IOR A D ADTRG Internal data bus PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data output timing signal Din Data bus input timing signal Figure B 31 PD31 D31 ADTRG Block Diagram ...

Page 895: ...DR Dn Dout Single mode MCU mode 1 MCU mode 0 MCU mode 2 PFC Q HIZ QPDnMD QPDnIOR Internal data bus n 8 15 PDR Port D read signal PDW Port D write signal RES Reset signal Dout Data output timing signal Din Data bus input timing signal SBYCR Figure B 32 PDn Dn Block Diagram ...

Page 896: ...MRES PEW RES Q D C PE13DR PER PFC SBYCR Q HIZ QPE13MD0 QPE13MD1 QPE13IOR SYSC MRES Internal data bus PER Port E read signal PEW Port E write signal RES Reset signal MTU TIOC4B TIOC4B Figure B 33 PE13 TIOC4B MRES Block Diagram ...

Page 897: ...K0 AH PEW RES Q D C PE14DR PER PFC SBYCR Q HIZ QPE14MD0 QPE14MD1 QPE14IOR Internal data bus PER Port E read signal PEW Port E write signal RES Reset signal MTU TIOC4C TIOC4C DRAK0 AH Figure B 34 PE14 TIOC4C DACK0 AH Block Diagram ...

Page 898: ...OUT PEW RES Q D C PE15DR PER PFC SBYCR Q HIZ QPE15MD0 QPE15MD1 QPE15IOR Internal data bus PER Port E read signal PEW Port E write signal RES Reset signal MTU TIOC4D TIOC4D DRAK1 IRQOUT Figure B 35 PEn TIOC4D DACK1 IRQOUT Block Diagram ...

Page 899: ...nMD QPEnIOR Internal data bus PER Port E read signal PEW Port E write signal RES Reset signal MTU TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A n 4 12 TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A Figure B 36 PEn TIOCXX Block Diagram ...

Page 900: ...RES Q D C PEnDR PER PFC SBYCR Q HIZ QPEnMD0 QPEnMD1 QPEnIOR Internal data bus PER Port E read signal PEW Port E write signal RES Reset signal MTU TIOC0B TIOC0D TIOC0B TIOC0D DRAKm n 1 3 m 0 1 Figure B 37 PEn TIOCXX DRAKm Block Diagram ...

Page 901: ...S Q D C PEnDR PER PFC SBYCR Q HIZ QPEnMD0 QPEnMD1 QPEnIOR DMA DREQm Internal data bus PER Port E read signal PEW Port E write signal RES Reset signal MTU TIOC0A TIOC0C TIOC0A TIOC0C n 0 2 m 0 1 Figure B 38 PEn TIOCXX DREQm Block Diagram ...

Page 902: ...864 Internal data bus Standby SBYCR Q HIZ AD ANn PFR PFn ANn n 0 7 PFR Port F read signal Figure B 39 PFn ANn Block Diagram ...

Page 903: ... Z 4 I Z I I I BACK Z 4 O Z O L L Interrupt NMI I I I I I I IRQ0 IRQ7 Z 4 I Z I I Z IRQOUT PD30 Z 4 O H 1 H O H 1 IRQOUT PE15 Z 4 O Z H O Z Address bus A0 A21 O 2 O Z O Z Z Data bus D0 D31 Z 4 I O Z I O Z Z Bus WAIT Z 4 I Z I Z Z control RD WR RAS Z 4 O O O Z Z CASH CASL CASLH CASLL Z 4 O O O Z Z RD H O Z O Z Z CS0 CS1 H O Z O Z Z CS2 CS3 Z 4 O Z O Z Z WRHH WRHL WRH WRL H O Z O Z Z AH Z 4 O Z O Z ...

Page 904: ... PF17 Z I Z I I Z Notes 1 There are instances where bus right release and transition to software standby mode occur simultaneously due to the timing between BREQ and internal operations In such cases standby mode results but the standby state may be different The initial pin states depend on the mode See section 18 Pin Function Controller for details 2 I Input O Output H High level output L Low le...

Page 905: ... L L Interrupt NMI I I I I I I IRQ0 IRQ7 Z 4 I Z I I Z IRQOUT Z 4 O Z H O Z Address bus A0 A21 O 2 O Z O Z Z Data bus D0 D31 Z 4 I O Z I O Z Z Bus WAIT Z 4 I Z I Z Z control RDWR RAS Z 4 O O O Z Z CASH CASL Z 4 O O O Z Z RD H O Z O Z Z CS0 CS1 H O Z O Z Z CS2 CS3 Z 4 O Z O Z Z WRH WRL H O Z O Z Z AH Z 4 O Z O Z Z DMAC DACK0 DACK1 Z 4 O Z O O Z DRAK0 DRAK1 Z 4 O Z O O Z DREQ0 DREQ1 Z 4 I Z I I Z MT...

Page 906: ...nd transition to software standby mode occur simultaneously due to the timing between BREQ and internal operations In such cases standby mode results but the standby state may be different The initial pin states depend on the mode See section 18 Pin Function Controller for details 2 I Input O Output H High level output L Low level output Z High impedance K Input pin with high impedance output pin ...

Page 907: ...H L L L L L L RD R H H H H H H W H H H H H WRHH R H H H H H H W H H H H H WRHL R H H H H H H W H H H H H WRLH R H H H H H H W H H H H H WRLL R H H H H H H W H H H H H A21 A0 Address Address Address Address Address Address D31 D24 High Z High Z High Z High Z High Z High Z D23 D16 High Z High Z High Z High Z High Z High Z D15 D8 High Z High Z High Z High Z High Z High Z D7 D0 High Z High Z High Z Hi...

Page 908: ... 2 H H H H CASHL 2 H H H H CASLH 2 H H H H CASLL 2 H H H H RD WR H H H H AH L L L L RD R L L L L W H H H H WRHH R H H H H W H H H H WRHL R H H H H W H H H H WRLH R H H H H W H L H L WRLL R H H H H W L H L L A21 A0 Address Address Address Address D31 D24 High Z High Z High Z High Z D23 D16 High Z High Z High Z High Z D15 D8 High Z Data High Z Data D7 D0 Data High Z Data Data ...

Page 909: ... H H H L H L WRHL R H H H H H H H W H L H H L H L WRH R H H H H H H H W H H L H H L L WRL R H H H H H H H W H H H L H L L A21 A0 Address Address Address Address Address Address Address D31 D24 Data High Z High Z High Z Data High Z Data D23 D16 High Z Data High Z High Z Data High Z Data D15 D8 High Z High Z Data High Z High Z Data Data D7 D0 High Z High Z High Z Data High Z Data Data Notes 1 R Read...

Page 910: ...L L L L W H H H H WRHH R H H H H W H H H H WRHL R H H H H W H H H H WRH R H H H H W H L H L WRL R H H H H W L H L L A21 A0 Address Address Address Address D31 D24 High Z High Z High Z High Z D23 D16 High Z High Z High Z High Z D15 D8 High Z Address Data Address Address Data D7 D0 Address Data Address Address Data Address Data Notes 1 R Read W Write 2 Valid High output in accordance with AH timing ...

Page 911: ...H H H CASLH 2 H Valid H Valid CASLL 2 Valid H Valid Valid RD WR R H H H H W L L L L AH L L L L RD R L L L L W H H H H WRHH R H H H H W H H H H WRHL R H H H H W H H H H WRH R H H H H W H L H L WRL R H H H H W L H L L A21 A0 Address Address Address Address D31 D24 High Z High Z High Z High Z D23 D16 High Z High Z High Z High Z D15 D8 High Z Data High Z Data D7 D0 Data High Z Data Data ...

Page 912: ...H H H WRHH R H H H H H H H W L H H H L H L WRHL R H H H H H H H W H L H H L H L WRH R H H H H H H H W H H L H H L L WRL R H H H H H H H W H H H L H L L A21 A0 Address Address Address Address Address Address Address D31 D24 Data High Z High Z High Z Data High Z Data D23 D16 High Z Data High Z High Z Data High Z Data D15 D8 High Z High Z Data High Z High Z Data Data D7 D0 High Z High Z High Z Data H...

Page 913: ...The values read from the internal registers for the flash ROM of the mask ROM version and F ZTAT version differ as follows Status Register Bit F ZTAT Version Mask ROM Version FLMCR1 FWE 0 Application software running 1 Programming 0 Is not read out 1 Application software running Note This difference applies to all the F ZTAT versions and all the mask ROM versions that have different ROM size ...

Page 914: ...8 HD6437041A F28 QFP2020 144 HD6437041A F version HD6437041AVF16 HD6437041A VF16 QFP2020 144 HD6437041A F HD6437041ACF28 HD6437041A CF28 QFP2020 144Cu 1 HD6437041A CF HD6437041AVCF16 HD6437041A VCF16 QFP2020 144Cu 1 HD6437041A CF ROM less A MASK HD6417041AF28 HD6417041AF28 QFP2020 144 HD6417041AF28 verion HD6417041AVF16 HD6417041AVF16 QFP2020 144 HD6417041AVF16 HD6417041ACF28 HD6417041ACF28 QFP202...

Page 915: ...ersion HD6437043AVF16 HD6437043A VF16 QFP2020 144 HD6437043A F HD6437043ACF28 HD6437043A CF28 QFP2020 144Cu 1 HD6437043A CF HD6437043AVCF16 HD6437043A VCF16 QFP2020 144Cu 1 HD6437043A CF Z TAT A MASK HD6477043AF28 HD6477043AF28 QFP2020 144 HD6477043AF28 version HD6477043AVF16 HD6477043AVF16 QFP2020 144 HD6477043AVF16 HD6477043ACF28 HD6477043ACF28 QFP2020 144Cu 1 HD6477043ACF28 HD6477043AVCF16 HD64...

Page 916: ...ensions of the SH7041 SH7043 SH7045 FP 144 are shown in figures F 4 and F 5 Package Code JEDEC JEITA Mass reference value FP 112 Conforms 2 4 g Dimension including the plating thickness Base material dimension 0 10 23 2 0 3 0 32 0 08 0 65 1 6 0 8 0 3 0 17 0 05 3 05 Max 23 2 0 3 84 57 56 29 112 1 28 20 85 2 70 0 8 0 13 M 0 10 0 15 0 10 1 23 0 30 0 06 0 15 0 04 Unit mm Figure F 1 Package Dimensions ...

Page 917: ...7 0 05 3 05 Max 23 2 0 2 84 57 56 29 112 1 28 20 85 2 70 0 8 0 13 M 0 10 0 15 0 10 1 23 0 30 0 06 0 15 0 04 Package Code JEDEC JEITA Mass reference value FP 112B Conforms 2 4 g Dimension including the plating thickness Base material dimension Unit mm Figure F 2 Package Dimensions FP 112B ...

Page 918: ...ms 0 5 g Dimension including the plating thickness Base material dimension 16 0 0 2 14 0 07 0 10 0 5 0 1 16 0 0 2 0 4 0 10 0 10 1 20 Max 0 17 0 05 0 8 90 61 1 30 91 120 31 60 M 0 17 0 05 1 0 1 00 1 2 0 15 0 04 0 15 0 04 Unit mm Figure F 3 Package Dimensions TFP 120 ...

Page 919: ... 4 g Dimension including the plating thickness Base material dimension 0 10 M 20 22 0 0 2 73 36 144 0 5 0 10 3 05 Max 0 8 22 0 0 2 108 72 37 109 1 0 17 0 05 2 70 0 22 0 05 0 5 0 1 1 0 0 10 0 15 0 10 1 25 0 20 0 04 0 15 0 04 Unit mm Figure F 4 Package Dimensions FP 144J ...

Page 920: ...e FP 144G Conforms 2 4 g Dimension including the plating thickness Base material dimension 0 10 M 20 22 0 0 2 73 36 144 0 5 0 10 3 05 Max 0 8 22 0 0 2 108 72 37 109 1 0 17 0 05 2 70 0 22 0 05 0 5 0 1 1 0 0 10 0 15 0 10 1 25 0 20 0 04 0 15 0 04 Unit mm Figure F 5 Package Dimensions FP 144G ...

Page 921: ...te 1st Edition February 1997 Rev 6 00 May 26 2003 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Renesas Kodaira Semiconductor Co Ltd 1997 2003 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 922: ...Colophon 0 0 http www renesas com Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan ...

Page 923: ...SH7040 SH7041 SH7042 SH7043 SH7044 SH7045 Group Hardware Manual REJ09B0044 0600O ...

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