Renesas SH7041 Series, Hardware Manual, Page: 33 / 923

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16.1.4 Register Configuration ......................................................................................... 570
16.2 Register Descriptions......................................................................................................... 571
16.2.1 A/D Data Register A–D (ADDRA0–ADDRD0, ADDRA1–ADDRD1) ............ 571
16.2.2 A/D Control/Status Register (ADCSR0, ADCSR1)............................................. 572
16.2.3 A/D Control Register (ADCR0, ADCR1) ............................................................ 574
16.3 Interface with CPU ............................................................................................................ 575
16.4 Operation ........................................................................................................................... 576
16.4.1 Single Mode (SCAN=0) ....................................................................................... 576
16.4.2 Scan Mode (SCAN=1) ......................................................................................... 578
16.4.3 Input Sampling and A/D Conversion Time .......................................................... 580
16.4.4 External Trigger Input Timing ............................................................................. 581
16.5 Interrupt and DMA, DTC Transfer Requests .................................................................... 582
16.6 A/D Conversion Precision Definitions .............................................................................. 583
16.7 Usage Notes ....................................................................................................................... 584
16.7.1 Analog Voltage Settings....................................................................................... 584
16.7.2 Handling of Analog Input Pins............................................................................. 584
Section 17 Compare Match Timer (CMT)
................................................................... 587
17.1 Overview............................................................................................................................ 587
17.1.1 Features................................................................................................................. 587
17.1.2 Block Diagram...................................................................................................... 587
17.1.3 Register Configuration ......................................................................................... 589
17.2 Register Descriptions......................................................................................................... 590
17.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 590
17.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 591
17.2.3 Compare Match Timer Counter (CMCNT) .......................................................... 592
17.2.4 Compare Match Timer Constant Register (CMCOR) .......................................... 593
17.3 Operation ........................................................................................................................... 593
17.3.1 Period Count Operation ........................................................................................ 593
17.3.2 CMCNT Count Timing......................................................................................... 594
17.4 Interrupts ............................................................................................................................ 594
17.4.1 Interrupt Sources and DTC Activation................................................................. 594
17.4.2 Compare Match Flag Set Timing ......................................................................... 594
17.4.3 Compare Match Flag Clear Timing ...................................................................... 595
17.5 Notes on Use ...................................................................................................................... 596
17.5.1 Contention between CMCNT Write and Compare Match ................................... 596
17.5.2 Contention between CMCNT Word Write and Incrementation........................... 597
17.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 598
Section 18 Pin Function Controller
................................................................................. 599
18.1 Overview............................................................................................................................ 599
18.2 Register Configuration....................................................................................................... 607
18.3 Register Descriptions......................................................................................................... 608