Renesas SH7041 Series, Hardware Manual, Page: 77 / 923

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Table 1.7 Pin Functions (cont)
Classification Symbol I/O Name Function
Bus control
(cont)
CASL
O Lower column
address strobe Timing signal for DRAM column
address strobe.
Output when the lower 8 bits of
data are accessed.
RDWR O DRAM
read/write DRAM write strobe signal.
AH
O Address hold Address hold timing signal for
devices using an address/data
multiplex bus.
WRHH
(QFP-144)
O HH write Indicates the writing of bits 31 to
24 of external data.
WRHL
(QFP-144)
O HL write Indicates the writing of bits 23 to
16 of external data.
CASHH
(QFP-144)
O HH column
address strobe Timing signal for DRAM column
address strobe. Output when bits
31 to 24 of data are accessed.
CASHL
(QFP-144)
O HL column
address strobe Timing signal for DRAM column
address strobe. Output when bits
23 to 16 of data are accessed.
Bus control
multifunction
timer/pulse unit TCLKA
TCLKB
TCLKC
TCLKD
I MTU timer
clock input Input pins for external clocks to
the MTU counter.
TIOC0A
TIOC0B
TIOC0C
TIOC0D
I/O MTU input
capture/ output
compare
(channel 0) Channel 0 input capture
input/output compare output/PWM
output pins.
TIOC1A
TIOC1B
I/O MTU input
capture/output
compare
(channel 1) Channel 1 input capture
input/output compare output/PWM
output pins.
TIOC2A
TIOC2B
I/O MTU input
capture/output
compare
(channel 2) Channel 2 input capture
input/output compare output/PWM
output pins.