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Lucent Technologies Inc.
3.2.2
X-Memory Space ............................................................................................................. 3-10
3.3
Arithmetic and Precision ................................................................................................................. 3-21
3.4
Interrupts......................................................................................................................................... 3-27
3.4.1
Introduction ...................................................................................................................... 3-27
3.4.2
Interrupt Sources ............................................................................................................. 3-29
3.4.3
Outputs of Interrupts ........................................................................................................ 3-31
3.4.4
Interrupt Operation ........................................................................................................... 3-32
3.4.5
Trap Description ............................................................................................................... 3-38
3.4.6
Powerdown with the AWAIT State .................................................................................... 3-40
3.4.7
Interrupts in DSP16A-Compatible Mode (DSP1617 Only) ............................................... 3-42
3.4.8
Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) ..................................... 3-44
3.5
Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only).......................................................... 3-47
3.5.1
PLL Control Signals ......................................................................................................... 3-48
3.5.2
PLL Programming Examples ........................................................................................... 3-50
3.5.3
Latency ............................................................................................................................ 3-50
3.6
Power Management ........................................................................................................................ 3-52
3.6.1
powerc Control Register Bits ........................................................................................... 3-52
3.6.2
STOP Pin ......................................................................................................................... 3-56
3.6.3
The pllc Register Bits (DSP1627/28/29 Only) ................................................................. 3-56
3.6.4
AWAIT Bit of the alf Register ........................................................................................... 3-56
3.6.5
Power Management Sequencing ..................................................................................... 3-57
3.6.6
Power Management Examples ........................................................................................ 3-58
4
Instruction Set ............................................................................................................................................. 4-1
4.1
Notation............................................................................................................................................. 4-2
4.2
Instruction Cycle Timing.................................................................................................................... 4-2
4.3
Addressing Modes ............................................................................................................................ 4-3
4.3.1
Register Indirect Addressing .............................................................................................. 4-3
4.3.2
Compound Addressing ...................................................................................................... 4-5
4.3.3
Direct Data Addressing ...................................................................................................... 4-7
4.4
Processor Flags ................................................................................................................................ 4-9
4.5
Instruction Set ................................................................................................................................. 4-11
4.5.1
Control Instructions .......................................................................................................... 4-12
4.5.2
Cache Instructions ........................................................................................................... 4-14
4.5.3
Data Move Instructions .................................................................................................... 4-15
4.5.4
Special Function Group ................................................................................................... 4-19
4.5.5
Multiply/ALU Group .......................................................................................................... 4-22
4.5.6
F3 ALU Instructions ......................................................................................................... 4-29
4.5.7
BMU Instructions .............................................................................................................. 4-30
4.5.8
Assembler Ambiguities ..................................................................................................... 4-35
5
Core Architecture ........................................................................................................................................ 5-1
5.1
Data Arithmetic Unit .......................................................................................................................... 5-1
5.1.1
Inputs and Outputs ............................................................................................................. 5-2
5.1.2
Multiplier Functions ............................................................................................................ 5-2
5.1.3
ALU .................................................................................................................................... 5-2
5.1.4
Accumulators ..................................................................................................................... 5-3
5.1.5
Counters ............................................................................................................................ 5-4
5.1.6
DAU Pseudorandom Sequence Generator (PSG) ............................................................. 5-7
5.1.7
Control Registers ............................................................................................................... 5-9
5.2
X Address Arithmetic Unit (XAAU) .................................................................................................. 5-11
5.2.1
Inputs and Outputs ........................................................................................................... 5-11
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...
