Information Manual
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Instruction Set
Lucent Technologies Inc.
DRAFT COPY
4-27
4.5 Instruction Set
(continued)
4.5.5 Multiply/ALU Group (continued)
Z : y
x = X The data from the specified X source is loaded into the x register. The data from the specified
Z source is loaded into the high half (bits 31—16) of the y register, and the old data from the high half of the
y register is loaded into the Z destination. If clearing of yl is enabled by using the CLR field of the auc register, yl
is cleared (0) when the high half is loaded.
Z : y The data from the specified Z source is loaded into the high half (bits 31—16) of the y register, and the old
data from the high half of the y register is loaded into the Z destination. If clearing of yl is enabled by using the
CLR field of the auc register, yl is cleared (0) when the high half is loaded. (See
.)
Z : yl The data from the specified Z source is loaded into the low half (bits 15—0) of the y register, and the old
data of the low half of the y register is loaded into the Z destination. Data in the high half of the y register is not
altered. (See Figure 4-3.)
Z : aT The data from the specified Z source is loaded into the high half (bits 31—16) of the specified accumula-
tor. If clearing of aTl is enabled by using the CLR field of the auc register, the low half of the accumulator is
cleared (0) when the high half is loaded. The guard bits (35—32) are loaded with the value of bit 31. The old
data from the high half of the accumulator is loaded into the Z destination. If saturation on overflow is enabled by
using the SAT field of the auc register, the transferred accumulator value is limited. (See
.)
Z : aTl The data from the specified Z source is loaded into the low half (bits 15—0) of the specified accumulator
and the old data from the low half of the accumulator is loaded into the Z destination. The data in the high half of
the accumulator is not altered. (See
.)
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...