Lucent Technologies DSP1611, Information Manual, Page: 100 / 443

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Software Architecture
Lucent Technologies Inc.
DRAFT COPY
3-47
3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
The DSP1627/28/29 provides an on-chip programmable clock synthesizer that can be driven by an external clock
at a fraction of the desired instruction rate.
Figure 3-19 is the clock source diagram. The 1X CKI input clock, the
output of the synthesizer, or a slow internal ring oscillator can be used as the source for the internal DSP clock.
The clock synthesizer is based on a phase-lock loop (PLL). The terms clock synthesizer and PLL are used inter-
changeably.
On powerup, CKI is used as the clock source for the DSP. This clock is used to generate the internal processor
clocks and CKO. Setting the appropriate bits in the pllc control register (see
Table 3-26 ) will enable the clock syn-
thesizer to become the clock source. The powerc register, which is discussed in Section 3.6.1, powerc Control
Register Bits , can be programmed to override the clock selection, to stop clocks, or to force the use of the slow ring
oscillator clock for low-power operation.
Notes:
Signals shown in bold are control bits from the pllc register or the powerc register.
If PLLSEL = 0, DSP runs from the 1X version of CKI input clock.
Other signals from the powerc register also control the clock source.
Figure 3-19. Clock Source Block Diagram
LOCK
PLL/SYNTHESIZER
pllc
powerc
f
CKI
Nbits[2:0]
Mbits[4:0]
LF[3:0]
÷
M
÷
N
PHASE
DETECTOR
LOOP
FILTER
CHARGE
PUMP
VCO
(FLAG TO INDICATE LOCK
CONDITION OF PLL)
VCO CLOCK
INTERNAL
PROCESSOR
CLOCK
PLLSEL
PLLEN
SLOWCKI
CKI INPUT CLOCK
÷
2
f
SLOW CLOCK
RING
OSCILLATOR
f
CKI
M
U
X
f
INTERNAL CLOCK
f
VCO