Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Core Architecture April 1998
5-10
DRAFT COPY
Lucent Technologies Inc.
5.1 Data Arithmetic Unit
(continued)
5.1.7 Control Registers (continued)
The accumulator guard bits are sign extended from bit 31 during data move instructions and, therefore, do not
affect the DAU flags. Writing the accumulator guard bits in the psw register will also change the corresponding bits
in the accumulator.
Table 5-4. Processor Status Word (psw) Register
Bit
15—12 11—10 9 8—5 4 3—0
Field
DAU Flags X a1[V] a1[35—32] a0[V] a0[35—32]
Bit(s) Field Value
†
† W indicates that the bit can be read or written.
Result/Description
15—12 DAU Flags
‡
‡ All DAU flags can be read from the psw register. The DAU flags are defined in section 3.1.4 , on page 3-7 .
Wxxx LMI logical minus if set.
xWxx LEQ logical equal if set.
xxWx LLV logical overflow if set.
xxxW LMV mathematical overflow if set.
11—10 X — Reserved.
9 a1[V] W Accumulator 1 (a1) overflow if set.
8—5 a1[35—32] Wxxx Accumulator 1 (a1) bit 35.
xWxx Accumulator 1 (a1) bit 34.
xxWx Accumulator 1 (a1) bit 33.
xxxW Accumulator 1 (a1) bit 32.
4 a0[V] W Accumulator 0 (a0) overflow if set.
3—0 a0[35—32] Wxxx Accumulator 0 (a0) bit 35.
xWxx Accumulator 0 (a0) bit 34.
xxWx Accumulator 0 (a0) bit 33.
xxxW Accumulator 0 (a0) bit 32.