Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
External Memory Interface April 1998
6-20
DRAFT COPY
Lucent Technologies Inc.
6.4 Timing Examples
(continued)
6.4.4 Read, Write, W = 0, Compound Address
Figure 6-6 illustrates a read followed by a write with zero wait-states. This example is generated by a compound
address instruction. Because only one external memory segment (ERAMLO) is being addressed, the ERAMLO
enable goes low at the beginning of the read cycle and stays low for the write cycle. The address bus (AB)
becomes valid with the read address at the beginning of the read cycle and changes to the write address at the
beginning of the write cycle. At some time in the read cycle, the data bus (DB) is driven by the external memory to
valid data that is latched into the DSP at the end of the read cycle. The data bus is 3-stated by the DSP at the
beginning of the write cycle and the external memory also 3-states. At the midpoint of the write cycle, the DSP
places data on the data bus and holds it for one period of CKO after the end of the write cycle to guarantee hold
time for the external memory unless immediately followed by a read cycle. The RWN signal is low for the duration
of the write cycle.
5-4165
Figure 6-6. Read, Write, W = 0
Sample Instruction:
*r0pz:y /* Compound read/write, r0 points to ERAMLO */
CKO
ERAMLO
DB
READ
DATA
RWN
READ CYCLE
W = 0
WRITE CYCLE
W = 0
AB
WRITE ADDRESS
WRITE DATA
READ
ADDR.