Information Manual
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Software Architecture
Lucent Technologies Inc.
DRAFT COPY
3-31
3.4 Interrupts
(continued)
3.4.2 Interrupt Sources (continued)
3.4.3 Outputs of Interrupts
The status bits in the ins register show if an interrupt has been recognized (defined as when the interrupt is latched
into the register). An interrupt, however, might be recognized but not serviced (acted on by executing the associ-
ated service routine) depending on the state of the machine (i.e., other interrupt in progress, uninterruptible instruc-
tion, etc.). An interrupt will not be serviced if not enabled. The VEC[3:0] outputs show the interrupt being serviced
(see the encoding in
). If no interrupt or trap is being serviced, the VEC[3:0] output pins are all zero.
Another output (IACK) goes high if any interrupt or trap is being serviced and goes low when the service routine
ends (see the functional timing diagrams for IACK timing).
Table 3-20. Vector Table
Source
Vector
Priority
VEC[3:0]
†
† Pins VEC[3:0] are multiplexed with pins IOBIT[7:4]. Bit 12 of the ioc register must be cleared to enable VEC[3:0].
Issued by
Cleared By
No interrupt
—
—
0x0
—
—
Software interrupt
0x2
1 lowest
0x1
icall
‡
‡ The icall instruction is reserved for use by the hardware development system.
ireturn
IBF enabled by pioc
§
§ Available on DSP1617 only.
0x1
1
0x1
SIO in
read of sdx
OBE enabled by pioc
0x1
1
0x1
SIO out
write to sdx
PIDS enabled by pioc
0x1
1
0x1
PIO in
read of pdx<0—7>
PODS enabled by pioc
0x1
1
0x1
PIO out
write to pdx<0—7>
INT0
0x1
2
0x2
pin
ireturn or write to ins
JINT
0x42
3
0x8
jtag in
read of jtag
INT1
0x4
4
0x9
pin
ireturn or write to ins
TIMEOUT
0x10
7
0xc
timer
ireturn or write to ins
IBF2
0x14
8
0xd
SIO2 in
read of sdx2
OBE2
0x18
9
0xe
SIO2 out
write to sdx2
Reserved
0x1c
10
—
—
—
EREADY
††
†† DSP1618/28 only.
0x20
11
0x1
ECCP ready
ireturn or write to ins
EOVF
0x24
12
0x2
ECCP overflow
ireturn or write to ins
Reserved
0x28
13
—
—
—
IBF enabled by inc
0x2c
14
0x3
SIO in
read of sdx
OBE enabled by inc
0x30
15
0x4
SIO out
write to sdx
PIDS/PIBF enabled by
inc
0x34
16
0x5
PHIF/PIO in
read of pdx0
PODS/POBE enabled by
inc
0x38
17
0x6
PHIF/PIO out
write to pdx0
TRAP from HDS
0x3
18
—
breakpoint, jtag, or pin
ireturn
TRAP from user
0x46
19 highest
0x7
pin
ireturn
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...