Lucent Technologies DSP1611, Information Manual, Page: 254 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Parallel I/O (DSP1617 Only) April 1998
8-16
DRAFT COPY
Lucent Technologies Inc.
8.2 Programmer Interface
(continued)
8.2.1 pioc Register Settings
Many of the bit fields in the pioc deal with interrupts. Before going any further the reader should be aware that in
addition to the interrupt control provided by the pioc, interrupts in the DSP1617 can be controlled through the inc
register in the CONTROL block. Because the PIO still supports interrupts to provide upward compatibility with the
DSP16A, the DSP1617 has a super set of interrupt features including vectored interrupts. A new application
should use the vectored interrupt features (see
Section 3.4, Interrupts ).
pioc Register Bit Descriptions
Bit 15 is the same as bit 4. See the description of bit 4 below.
Bits 14 and 13 control the duration of assertion of the PIDS and PODS signals. (This is described in more detail
in
Section 8.1.1, Active Mode .)
Bit 12, if equal to logic 1, makes the PODS pin an output; accordingly, the DSP can perform active mode write
transactions to external devices. If bit 12 of the pioc register is equal to logic 0, the PODS pin is an input used by
external devices to request the DSP to write.
Bit 11, if equal to logic 1, makes the PIDS pin an output; accordingly, the DSP can perform active mode read
transactions from external devices. If bit 11 of the pioc register is equal to logic 0, the PIDS pin is an input used
by external devices to request the DSP to read the bus.
Bits 9—5 are used to enable/disable interrupts. These bits will only disable interrupts if they are not enabled in
the inc (see
Section 3.4, Interrupts ).
Bits 4—0 indicate the status of the two SIO interrupts (IBF and OBE), the two PIO interrupts (PIDS and PODS),
and the INT0 pin. This portion of the pioc register determines which of the interrupts are requesting service.
These bits can be read by an interrupt service routine to determine which interrupt(s) have occurred and, there-
fore, how to proceed to service the interrupt request. These status bits are also used to perform programmed
I/O by polling some condition if necessary.
Section 8.3, Interrupts and the PIO , has more detail on PIO inter-
rupts.
Powerup and Reset: The contents of the pioc register are cleared, except bit 3 which is set if the RSTB signal is
asserted. Accordingly, the DSP is in passive mode with all interrupts masked after a device reset.