Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Instruction Set Summary
Lucent Technologies Inc.
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B-12
aT[l] = R
(load accumulator from register)
(aT[l])
←
(R)
The contents of accumulator aT (bits 31—16) or aTl (bits 15—0) are replaced with the current contents of register
R, which are zero- or sign-extended to 16 bits if necessary. If clearing of aTl is enabled on a write to aT (with the
CLR field of the auc register), bits 15—0 of accumulator aT will be cleared. Bits 35—32 (the guard bits) will be
loaded with copies of bit 31.
The value of X can be zero to select aT or one to select aTl.
The value of aT can be zero to select a1 or one to select a0. aT is encoded as aT in the instruction encodings in
Appendix A. Register R is one of the general sets of registers shown (in Table B-2 on page B-8 ) for the long imme-
diate load, except that registers sioc, sioc2, srta, srta2, tdms, and tdms2 are not readable.
Note: If y or p is used as the register R, the assembler forces a special function encoding. The resulting instruction
moves all 32 bits (sign-extended to 36 bits) of y into aT. All DAU flags are affected, and the execution
requires only one cycle. If a two-cycle data move is desired, the optional mnemonic move may be used.
Only the upper 16 bits of y are transferred and no flags are affected. For example:
move a0 = y
Bit
15 14 13 12 11 10 9—4 3 2 1 0
Field 0 1 0 0 0 aT R 0 0 0 X
Words: 1
Cycles: 2
Group: Data Move
Addressing: Register
Flags affected: None
Interruptible: Yes
Cacheable: Yes
Format: 7a