Lucent Technologies DSP1611, Information Manual, Page: 78 / 443

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Software Architecture
Lucent Technologies Inc.
DRAFT COPY
3-25
3.3 Arithmetic and Precision
(continued)
Shift Left 2 Bits (Figure 3-6)
If the auc[1:0] bits are 10, the data in the p register is shifted 2 bits to the left with respect to the bits in the accumu-
lator as product bits 31—0 are transferred into bits 33—2 of the accumulator. Bits 1 and 0 of the accumulator are
cleared by the load of the accumulator with the data in p. The sign of p is extended by 2 bits into bits 35 and 34 of
the accumulator. This mode is often used in filtering applications where coefficients in the x register are in Q14 for-
mat (2 magnitude bits, 14 fractional bits), and state variables in the y register are 16-bit integers. If the p register is
not shifted prior to accumulation, the accumulated result would have 4 guard bits, 18 magnitude bits, and 14 frac-
tional bits. Because it is often desirable to have the implied binary point to the right of bit 16 (16 fractional bits), the
setting auc[1:0] = 10 automatically shifts the result 2 bit locations to the left generating an accumulated result with
4 guard bits, 16 magnitude bits, and 16 fractional bits.
Note: The top 2 magnitude bits are shifted into overflow bits 33 and 32 that can only be read via the psw register,
and saturation can be detected if enabled in the auc register.
5-4114
Figure 3-6. p Register to Accumulator Bit Alignment, auc[1:0] = 10
x(16)
15 0
31 16 15
y(32)
p(32)
a0, a1(36)
0
31
35
2 33 1 0