Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Software Architecture
Lucent Technologies Inc.
DRAFT COPY
3-21
3.3 Arithmetic and Precision
Fixed-point, two's complement arithmetic is used throughout the DSP1611/17/18/27/28/29 device. In the DAU,
16-bit data in the x register and in the high half of the y register can be multiplied together and the 32-bit result is
stored in the p register. The data in the y or p registers or both accumulators can be operated on by the ALU; the
result is stored in either of the 36-bit accumulators. The 32-bit data from the y or p register is sign-extended to
36 bits if operated on by the ALU. The four guard bits in the accumulators reduce the need for scaling data.
Sometimes the 36-bit accumulators can be thought of as having an implied binary point to the right of bit 16, for
example, if multiplying a fraction with 16 bits to the right of the decimal (Q16 format) times an integer. Bits
15—0 are then the fractional part (which is referred to as aMI, where aM
= a0 or a1), and bits 35—16 are the inte-
ger part. The ALU operates on all 36 bits of the accumulators. The CLR field of the auc register (see Table 3-10 )
controls automatic clearing of the low half while loading a0, a1, or y registers. This makes it easy to perform 16-bit
integer operations in the ALU by automatically clearing the low half of the register when the high half is loaded.
The operands for the DAU can have many different formats. To make it easier to handle these different formats, the
DSP has four options for scaling data as it is transferred from the p register to the accumulators: no shift, a 2-bit left
shift, 1-bit left shift, or a 2-bit right shift.
Table 3-10 illustrates how 2 bits in the auc register (auc[1, 0]) determine
the bit alignment of the data in p with respect to the data in the accumulators. The connection of the data bus to
the p register, the RAM, the accumulators, and the remaining registers in the DSP device is fixed, i.e., no other
automatic shifts of data occur with data move or multiply/ALU instructions (although effectively a 16-bit right shift
occurs in transferring the high half of a 32-bit register to a 16-bit register).
The SAT field of the auc register (bits 3, 2) selects or deselects saturation mode. This is the manner in which data
is transferred from the accumulators after an overflow has been detected. Overflow occurs whenever bit 31 of an
accumulator is different from any of its guard bits.
If saturation is enabled, the data transferred out of the accumulator is the largest positive or negative number (as
defined by bit 35 of the accumulator) that can be represented with 32 bits.
Note: The data in the accumulator does not change, only the value that is transferred changes.
2
31
– 1 = 0x7FFFFFFF largest positive number
–2
31
= 0x80000000 largest negative number
In nonsaturation mode, the actual value in the accumulator will be written.
For further information about overflow, refer to the psw register in Section 5.1.7, Control Registers .
The X=Y= field of the auc register (bit 7) controls the loading of the x register. If this bit is set to zero, there is no
change in the loading of the x register; i.e., instructions that load the x register operate as expected, and instruc-
tions that do not load the x register do not affect the contents of the x register. If this bit is set to one, all instruc-
tions that load the high half of the y register cause the same data that is loaded into y to be loaded into x. The
purpose of this bit is to allow a single-cycle squaring operation. For example:
a0=0
auc=0x80 /* enable X=Y= */
r1=table
y=*r1++ /* square, and load both y and x */
do 100 {
a0=a0+p
p=x*y
y=*r1++ /* accumulate, square, and load both y */
/* and x */
auc=0 /* disable X=Y= */