Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Core Architecture
Lucent Technologies Inc.
DRAFT COPY
5-9
5.1 Data Arithmetic Unit
(continued)
5.1.7 Control Registers
In addition to the registers already mentioned, the user has access to the arithmetic unit control register (auc) and
the processor status word register (psw). The auc register configures some features of the data arithmetic unit as
described in
Table 5-3 . The auc register is cleared to all zeros at reset. Bits 11 and 10 of the psw are cleared at
reset.
The psw register contains status information from the data arithmetic unit as shown in Table 5-4 . The psw register
is normally read to get status information. However, if it is overwritten, the new information will be considered valid.
Note: There is no capability to write just one or a few bits; all 16 bits have to be written.
psw bits 9 and 4 are ones if a 32-bit overflow occurs from an accumulator calculation for a0 and a1, respectively.
A 32-bit overflow or mathematical overflow occurs if the result of a DAU add/subtract or BMU shift operation cannot
be properly expressed in 32 bits (the sign bit rolls over into bit 33). The accumulator guard bits will then differ from
the sign bit (bit 31). Also, a logical overflow can be detected in the psw register on bit 13 (LLV). A logical overflow
occurs if a number cannot be expressed in 36 bits (36-bit overflow). This can happen if any significant bits are lost
after adding, subtracting, or shifting overflow numbers.
The psw register contains the status of two additional DAU flags: LEQ and LMI. The LEQ (psw[14]) bit is set if the
last DAU/BMU operation produces a result of zero (all 36 bits in the accumulator can be zero). The LMI (psw[15])
bit is set if the last DAU/BMU operation produces a negative number as determined by accumulator bit 35. If bit 35
equals one, the result is negative; but if bit 35 equals zero, the result is positive.
Table 5-3. Arithmetic Unit Control (auc) Register
Bit
15—9 8 7 6—4 3—2 1—0
Field reserved RAND X=Y= CLR SAT ALIGN
Field Value Description
reserved — Reserved
†
† The auc is a 16 bit register of which 9 bits [8:0] are used for control. The unused upper 7 bits [15:9] are always zero if read and should always
be written with zeros to make the program compatible with future chip versions. The auc register is cleared at reset.
RAND 0 Pseudorandom sequence generator (PSG) reset by writing the pi register only
outside an interrupt service routine.
1 PSG never reset by writing the pi register.
X=Y= 0 Normal operation.
1 y = Y transfer statements load both the x and the y registers, allowing single
cycle squaring with p = x * y.
CLR 1xx Clearing yl is disabled (enabled if 0).
x1x Clearing a1l is disabled (enabled if 0).
xx1 Clearing a0l is disabled (enabled if 0).
SAT 1x a1 saturation on overflow is disabled (enabled if 0).
x1 a0 saturation on overflow is disabled (enabled if 0).
ALIGN 00
a0, a1
←
p.
01 a0, a1
←
p/4.
10 a0, a1
←
p x 4 (and zeros written to the two LSBs).
11
a0, a1
←
p x 2 (and zeros written to the two LSBs).