Lucent Technologies DSP1611, Information Manual, Page: 104 / 443

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Software Architecture
Lucent Technologies Inc.
DRAFT COPY
3-51
3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
(continued)
3.5.3 Latency (continued)
Table 3-26. Phase-Locked Loop Control (pllc) Register
Bit 15 14 13 12 11—8 7—5 4—0
Field PLLEN PLLSEL ICP SEL5V
†
LF[3:0] Nbits[2:0] Mbits[4:0]
Field Value Description
PLLEN 0
1 PLL powered down.
PLL powered up.
PLLSEL 0
1 DSP internal clock taken directly from CKI.
DSP internal clock taken from PLL.
ICP — Charge Pump Current Selection (see Table 3-27 for proper value).
SEL5V
†
0
1 3 V operation (see Table 3-27 for proper value).
5 V operation (see Table 3-27 for proper value).
LF[3:0] — Loop filter setting (see Table 3-27 for proper value).
Nbits[2:0] — Encodes N, 1
≤
N
≤
8; where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111 then N = 1.
Mbits[4:0] — Encodes M, 2
≤
M
≤
24; where M = Mbits[4:0] + 2 & f
INTERNAL CLOCK
= f
CKI
x (M/(2N)).
† Not available on the DSP1628 or DSP1629.
Table 3-27. PLL Electrical Specifications and pllc Register Settings
M V
DD
pllc13
(ICP)
pllc12
(SEL5V)
pllc[11:8]
(LF[3:0])
Typical Lock-in Time (
µ
s)
(See Note 2)
23—24 2.7 V—3.6 V 1 0 1011 30
21—22 2.7 V—3.6 V 1 0 1010 30
19—20 2.7 V—3.6 V 1 0 1001 30
16—18 2.7 V—3.6 V 1 0 1000 30
12—15 2.7 V—3.6 V 1 0 0111 30
8—11 2.7 V—3.6 V 1 0 0110 30
2—7 2.7 V—3.6 V 1 0 0100 30
19—20 5 V
±
5% 1 1 1110 30
17—18 5 V
±
5% 1 1 1101 30
16 5 V
±
5% 1 1 1100 30
14—15 5 V
±
5% 1 1 1011 30
12—13 5 V
±
5% 1 1 1010 30
10—11 5 V
±
5% 1 1 1001 30
8—9 5 V
±
5% 1 1 1000 30
7 5 V
±
5% 1 1 0111 30
5—6 5 V
±
5% 1 1 0110 30
2—4 5 V
±
5% 1 1 0101 30
Notes:
The M and N counter values in the pllc register must be set so that the VCO operates in the appropriate range
(see the data sheet). Choose the lowest value of N and then the appropriate value of M for
f
INTERNAL CLOCK
= f
CKI
x (M/(2N)) = f
VCO
/2.
Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which the PLL out-
put clock is unstable. The DSP must operate from the 1X CKI input clock or from the slow ring oscillator while the
PLL is locking. Completion of the lock-in interval is indicated by assertion of the LOCK flag.