Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture April 1998
3-38
DRAFT COPY
Lucent Technologies Inc.
3.4 Interrupts
(continued)
3.4.4 Interrupt Operation (continued)
Polling for Interrupt
The interrupts that are masked will not be serviced by an interrupt service routine. However, the interrupt condi-
tions can be determined by polling the ins register. If the interrupt source is examined in a polling routine, certain
action is taken to clear that status bit in the ins register. The SIO[2] and PIO/PHIF interrupt conditions can be
cleared by reading or writing the I/O registers. JINT can be cleared by reading the jtag register. The interrupts
TIME and INT[1:0] are cleared by an ireturn instruction or by writing the corresponding bits of the ins register with
ones. Interrupts that can be cleared by an ireturn instruction are latched on the rising edge of the IACK signal. For
this reason, these interrupts cannot be polled while programs are executing from the interrupt level.
In the following example, the code continuously polls the ins register to determine if the condition TIMEOUT is true.
When the timer reaches zero count, the serial input data is read into RAM and the TIMEOUT status of the ins reg-
ister is cleared.
sioc=0x0 /* passive SIO */
inc=0x0 /* mask vectored interrupts */
wait: a0=ins /* check ins register for TIMEOUT */
a0h&0x0100 /* look only at bit 8 */
if eq goto wait /* if no TIMEOUT, wait. */
ins=0x0100 /* if TIMEOUT, clear interrupt by setting bit 8 to 1 */
*r0=sdx /* move serial input data into RAM */
Note: pioc bits 9, 8 = 0 to disable ibf and obe interrupts in DSP16A-compatible mode (DSP1617 only).
3.4.5 Trap Description
The maximum interrupt latency in a program can be as long as thousands of cycles if a cache loop uses a large
repeat count. For some time-critical events, the long interrupt response time is too slow to gain control of the pro-
cessor and remove the exception condition. Therefore, programming techniques such as breaking long cache
loops into several short ones, using short interrupt service routines, etc. are often used to improve the response
time. Alternatively, the trap mechanism causes the processor to branch to a trap service routine with less than four
cycles of latency without restrictions from the current instruction. If in a trap service routine, another trap will be
ignored. Also, the trap feature is used by the hardware development system for breakpointing and gaining control
of the processor.
Table 3-20 shows the vector address, priority, and trap status encoding (VEC[3:0]) of the user
trap and HDS trap.
The user trap (vector 0x46) is caused by asserting the TRAP pin of the DSP. Because a trap is not maskable and
the user trap has the highest priority, at most two instructions (four cycles maximum) will execute from the time the
trap is received at the pin to when it gains control (see
Figure 3-14 ). An instruction that is executing when the trap
occurs will be allowed to complete before the trap is taken (note that the instruction could be lengthened by wait-
states). If the instruction is a two-cycle instruction (not counting wait-states), the pi register contains the address of
the next instruction. If the instruction was a one-cycle instruction, the pi register will contain the address after the
next instruction. If the program is in an interrupt service routine at the time the trap was taken, the return address
in the pi register is overwritten if a user trap is taken. It is not possible to return to an interrupt service routine from
a user trap service routine. Continuing program execution if a trap occurs during a cache loop is also not possible.
A trap by the hardware development system does not affect the IACK or VEC[3:0] pins. Instead, they show the
interrupt state or interrupt source of the DSP when the TRAP occurs.