Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture April 1998
3-50
DRAFT COPY
Lucent Technologies Inc.
3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
(continued)
3.5.2 PLL Programming Examples
The following section of code illustrates how the PLL is initialized on powerup assuming the following operating
conditions:
V
DD
= 3 V
CKI input frequency = 10 MHz
Internal clock and CKO frequency = 50 MHz
VCO frequency = 100 MHz
Input divide down count N = 2 (Set Nbits[2:0] = 000 to get N = 2, as Table 3-26 describes.)
Feedback down count M = 20 (Set Mbits[4:0] = 10010 to get M = 18 + 2 = 20, as Table 3-26 describes.)
The device comes out of reset with the PLL powered down and deselected.
pllinit: pllc=0xA912 /* Running CKI input clock at 10 MHz, set up counters
*/
/* in PLL, Power on PLL, but PLL remains deselected
*/
call pllwait /* Loop to check for LOCK flag assertion */
pllc=0xE912 /* Select high-speed, PLL clock */
2*nop /* Switch to PLL latency */
goto start /* User’s code, now running at 50 MHz */
pllwait: if lock return
goto pllwait
Section 3.6.6, Power Management Examples lists programming examples that illustrate how to use the PLL with
the various power management modes.
3.5.3 Latency
The switch between the CKI-based clock and the PLL-based clock is synchronous. This method results in the
actual switch taking place several cycles after the PLLSEL bit is changed. During this time, actual code can be
executed at the precedent clock rate.
Table 3-25 shows the latency times for switching between CKI-based and
PLL-based clocks. The PLL cannot be disabled until the switch back to CKI has been completed. In the example
given, the delay to switch to the PLL source is 1—4 CKO cycles and to switch back is 11—31 CKO cycles.
Table 3-25. Latency Times for Switching Between CKI and PLL-Based Clocks
Minimum
Latency (cycles)
Maximum
Latency (cycles)
Switch to PLL-based clock 1 N + 2
Switch from PLL-based clock M/N + 1 M + M/N + 1