DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Information Manual
Software Architecture
April 1998
3-8
DRAFT COPY
Lucent Technologies Inc.
3.2 Memory Space and Addressing
The DSP1611/17/18/27/28/29 has two memory spaces: the X-memory space and the Y-memory space. They are
differentiated by which addressing unit they use and not by the physical memory they use. The dual-port RAM is in
the Y space and the X space, but it can be at different addresses. The Y addressing arithmetic unit (YAAU), unique
to the Y-memory space, is particularly suited for addressing memory that contains data or operands for the pro-
cessing units. The X addressing arithmetic unit (XAAU), unique to the X-memory space, is particularly suited for
program control and addressing memory that contains the instructions and coefficients as operands.
The internal dual-port RAM can be accessed in both the Y space and the X space. This RAM has multiple 1 Kword
banks, and, as long as the banks accessed are different, simultaneous data and instruction accesses can be
made. If the same bank is accessed from both memory spaces simultaneously, an extra instruction cycle (one
wait-state) is added to carry out the transfer and the Y space transfer is performed before the X space transfer.
3.2.1 Y-Memory Space
The Y-memory space is shown in
. Associated with the Y space are the Y addressing arithmetic unit
(YAAU), the Y address bus (YAB), the Y data bus (YDB), and the external memory interface (EMI). The 64K mem-
ory space is divided into four segments (RAM, IO, ERAMLO, and ERAMHI), as shown in
. The selection
of a segment is automatic corresponding to the address in the YAAU. The segment for the internal RAM is further
divided into multiple 1K banks. The addresses are decoded in the YAAU, and an enable wire is provided for each
of the three external segments and for each of the internal RAM banks.
5-4110
Figure 3-2. Data (Y) Memory Space
INTERNAL
DUAL-PORT
RAM
YAAU
EXTERNAL
ERAMHI
EXTERNAL
ERAMLO
EXTERNAL
IO
YDB DATA BUS
YAB
EXTERNAL MEMORY DATA BUS
OFF-CHIP
EXTERNAL MEMORY ADDRESS BUS
EN
ABL
ES
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...