Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Hardware Architecture April 1998
2-12
DRAFT COPY
Lucent Technologies Inc.
2.1 Device Architecture Overview
(continued)
2.1.4 Memory Space and Bank Switching
Table 2-3 describes the two memory spaces.
There are two memory spaces with separate addressing units, address buses, and data buses. The actual memo-
ries associated with the spaces are enabled automatically based on the address. For the data memory space,
either internal dual-port RAM or external memory is used. The external memory is divided into three segments.
The internal dual-port RAM is divided into multiple 1K word banks for DSP1611/17/18/27/28/29. For the program
memory space, either internal ROM, internal dual-port RAM, or external ROM can be addressed. There are
2
16
= 65,536 addresses in each of the two memory spaces; the total address space for each is divided into seg-
ments, and each segment is associated with a physical memory. The arrangement of the segments is called the
memory map. There is one map for the data memory space, and there are four possible memory maps for the pro-
gram space. Memory maps are discussed in
Section 3.2, Memory Space and Addressing and Section 6.1, EMI
Function .
Table 2-3. Memory Space
Terminology Address
Source
Address
Bus
Memory Segments
Accessed
Data Bus
Data (Y) memory space (see Section
3.2.1 ).
YAAU YAB RAM[1:x]
†
† x = 4 for DSP1617 and DSP1618.
x = 6 for DSP1627.
x = 8 for DSP1628x08.
x = 10 for DSP1629x10.
x = 12 for DSP1611.
x = 16 for DSP1628x16 and DSP1629x16.
YDB
IO
ERAMLO
ERAMHI
Program or instruction/coefficient (X)
memory space (see
Section 3.2.2 ).
XAAU XAB [RAM1:x]
†
XDB
IROM
EROM