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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR

Information Manual

Hardware Architecture

April 1998

2-4

DRAFT COPY

Lucent Technologies Inc.

2.1 Device Architecture Overview

(continued)

2.1.3 Device Architecture

show the block diagrams for DSP1611, DSP1617, DSP1618, DSP1627,

DSP1628, and DSP1629 processors. The major blocks are the DSP1600 processor core, the memories, the bit
manipulation unit, the external memory interface, the serial input(s)/output(s), the parallel input/output, the bit I/O,
the JTAG, and the timer.

† These registers are accessible through external pins only.

5-4142.a

Figure 2-3. DSP1611 Block Diagram

TDO

TCK

TMS

M
U
X

DSP1600 CORE

RWN

EXM

DSEL

EROM ERAMHI

AB[15:0]

DB[15:0]

I/O

VEC[3:0] OR IOBIT[7:4]

DO2 OR PSEL1

OLD2 OR PODS

OCK2 OR PSEL2

OBE2 OR POBE

SYNC2 OR PSEL0

ICK2 OR PB0

ILD2 OR PIDS

DI2 OR PB1

IBF2 OR PIBF

DOEN2 OR PB2

SADD2 OR PB3

IOBIT[3:0] OR PB[7:4]

CKI

CKI2
CKO

RSTB

STOP

TRAP

INT[1:0]

IACK

DI1

ICK1

ILD1

IBF1

DO1

OCK1

OLD1

OBE1

SYNC1

SADD1

DOEN1

EXTERNAL MEMORY INTERFACE & EMUX

ioc

DUAL-PORT

RAM

12K x 16

ROM

1K x 16

ERAMLO

YAB

YDB

XDB

XAB

BMU

aa0

aa1

ar0

ar1

ar2

ar3

IDB

PHIF

phifc

PSTAT

†

pdx0(IN)

pdx0(OUT)

BIO

sbit

cbit

SIO2

sdx2(OUT)

srta2

tdms2

sdx2(IN)

sioc2

saddx2

SIO1

sdx(OUT)

srta

tdms

sdx(IN)

sioc

saddx

TIMER

timerc

timer0

HDS

BREAKPOINT

†

JTAG

BOUNDARY-SCAN

jtag

JCON

†

ID

†

BYPASS

†

TRACE

†

powerc

TDI

«
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30
31
32
33
34
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Summary of Contents for DSP1611

Page 1: ...Shan Xi Road Shanghai 200233 P R China Tel 86 21 6440 0468 ext 316 FAX 86 21 6440 0652 JAPAN Microelectronics Group Lucent Technologies Japan Ltd 7 18 Higashi Gotanda 2 chome Shinagawa ku Tokyo 141 Ja...

Page 2: ...is a registered trademark of The Institute of Electrical and Electronics Engineers Inc Intel is a registered trademark of Intel Corporation Motorola is a registered trademark of Motorola Inc MS DOS an...

Page 3: ...ls are also available to aid in developing soft ware and integrating the devices into systems Additional information on the digital signal processor product line is available in the form of manuals da...

Page 4: ...iew 2 16 2 2 1 Data Arithmetic Unit 2 16 2 2 2 Y Space Address Arithmetic Unit YAAU 2 17 2 2 3 X Space Address Arithmetic Unit XAAU 2 18 2 2 4 Cache 2 18 2 2 5 Control 2 18 2 3 Internal Memories 2 19...

Page 5: ...f the alf Register 3 56 3 6 5 Power Management Sequencing 3 57 3 6 6 Power Management Examples 3 58 4 Instruction Set 4 1 4 1 Notation 4 2 4 2 Instruction Cycle Timing 4 2 4 3 Addressing Modes 4 3 4 3...

Page 6: ...Delayed Enable 6 23 6 4 8 Write Read with Delayed Enable 6 24 6 5 Boot Up from External ROM 6 25 6 6 Memory Sequencer 6 26 6 7 Downloading Code into External Program Memory 6 28 7 Serial I O 7 1 7 1...

Page 7: ...rammer Interface 9 8 9 2 1 phifc Register Settings 9 8 9 2 2 Power Management 9 10 9 3 Interrupts and the PHIF 9 10 9 4 PHIF Pin Multiplexing 9 11 9 5 Overall Functional Timing 9 12 10 Bit I O Unit 10...

Page 8: ...traction 13 5 13 2 5 Insertion 13 6 13 2 6 Shuffle Accumulators 13 8 13 2 7 Instruction Encoding 13 9 13 2 8 Software Example 13 10 14 Error Correction Coprocessor DSP1618 28 Only 14 1 14 1 System Des...

Page 9: ...rogrammable Options 15 14 15 4 1 Input Clock Options 15 14 15 4 2 ROM Security Options DSP1617 18 27 28 29 Only 15 14 15 5 Additional Electrical Characteristics and Requirements for Crystal 15 15 A In...

Page 10: ...B 40 aD aS OP aT B 42 aD aS OP p B 43 aD aS h l OP IM16 B 44 aD a SHIFT aS B 46 aD aS SHIFT arM B 47 aD aS SHIFT IM16 B 48 aD exp aS B 49 aD norm aS arM B 50 aD extracts aS arM B 51 aD extractz aS arM...

Page 11: ...of a Simple Interrupt 3 33 Figure 3 11 Interrupt Disable Latency 3 35 Figure 3 12 Interrupt Request Circuit Diagram 3 36 Figure 3 13 Timing Diagram of Concurrent Interrupts 3 37 Figure 3 14 Timing Di...

Page 12: ...611 17 18 27 28 29 to Lucent Technologies CSP1027 Codec Interface 7 13 Figure 7 10 DSP1611 17 18 27 28 29 to Lucent Technologies T7525 Codec Interface 7 13 Figure 7 11 Multiprocessor Connections 7 15...

Page 13: ...igure 11 7 Bidirectional Cell 11 14 Figure 11 8 Cell Interconnections for a Bidirectional Pin 11 15 Figure 11 9 The Device Identification Register JIDR 11 16 Figure 12 1 Timer Block Diagram 12 1 Figur...

Page 14: ...ory Map X Memory Space 3 16 Table 3 15 DSP1628x16 Instruction Coefficient Memory Map X Memory Space 3 17 Table 3 16 DSP1629x10 Instruction Coefficient Memory Map X Memory Space 3 18 Table 3 17 DSP1629...

Page 15: ...emory Map X Memory Space 6 4 Table 6 3 DSP1618 Instruction Coefficient Memory Map X Memory Space 6 4 Table 6 4 DSP1618x24 Instruction Coefficient Memory Map X Memory Space 6 5 Table 6 5 DSP1627 Instru...

Page 16: ...at 3b BMU Operations 13 9 Table 14 1 Incremental Branch Metrics 14 4 Table 14 2 ECCP Instruction Encoding 14 9 Table 14 3 Reset State of ECCP Registers 14 9 Table 14 4 Memory Mapped Registers 14 10 Ta...

Page 17: ...Lucent Technologies Inc xvii Table A 17 X Field A 10 Table A 18 Y Field A 10 Table A 19 Z Field A 10 Table B 1 CON Field Encoding B 3 Table B 2 R Field Replacement Values B 8...

Page 18: ...Chapter 1 Introduction...

Page 19: ...al Description 1 2 1 1 1 Architecture 1 2 1 1 2 Instruction Set 1 3 1 2 Typical Applications 1 3 1 3 Application Support 1 4 1 3 1 Support Software Library 1 4 1 3 2 Hardware Development System 1 4 1...

Page 20: ...internal ROM and internal dual port RAM configurations Dual serial I O ports with multiprocessor capability 16 bit data channel 8 bit protocol channel 8 bit parallel interface 8 bit control I O inter...

Page 21: ...se use of the cache eliminates a memory access for instruction fetches Two addressing units support high speed register indirect memory addressing with postincrementing of the regis ter Four address p...

Page 22: ...timal matching to system requirements several options for low voltage power supply and clock speeds are available See the latest data sheet for the current offerings 1 1 2 Instruction Set The DSP1611...

Page 23: ...e code into object code in a standard format COFF that is then processed by the linker The assembler contains a preprocessor similar to the C preprocessor and pro vides the features of a full macro as...

Page 24: ...executed at full speed The emulation is performed with the actual DSP located on the user s board and not one separated from it by a performance limiting cable Program development with breakpointing...

Page 25: ...ses Chapter 5 Core Architecture A detailed description of the DSP1600 core architecture Chapter 6 External Memory Interface A description of the EMI port including functional timing Chapter 7 Serial I...

Page 26: ...ruction set and interfacing requirements DSP1611 DSP1617 DSP1618 DSP1627 DSP1628 and DSP1629 Digital Signal Processor data sheets provide up to date timing requirements and specifications electrical c...

Page 27: ...Chapter 2 Hardware Architecture...

Page 28: ...Space Address Arithmetic Unit YAAU 2 17 2 2 3 X Space Address Arithmetic Unit XAAU 2 18 2 2 4 Cache 2 18 2 2 5 Control 2 18 2 3 Internal Memories 2 19 2 4 External Memory Interface EMI 2 19 2 5 Bit M...

Page 29: ...e Y memory space Each memory space has a corresponding address arithmetic unit In the instruction coefficient memory space the program addressing unit XAAU places addresses on the program address bus...

Page 30: ...tween the RAM and the DAU It could alter natively have been addressing the ROM to transfer fixed coefficients to the DAU The data addressing unit YAAU is addressing another bank of the dual port RAM B...

Page 31: ...ion pointed to by the address in the pt register and postincrement the address p x y means multiply the data in registers x and y and put the result in register p a0 a0 p means add the value in p to t...

Page 32: ...ough external pins only 5 4142 a Figure 2 3 DSP1611 Block Diagram TDO TCK TMS M U X DSP1600 CORE RWN EXM DSEL EROM ERAMHI AB 15 0 DB 15 0 I O VEC 3 0 OR IOBIT 7 4 DO2 OR PSEL1 OLD2 OR PODS OCK2 OR PSE...

Page 33: ...BE2 OR POBE SYNC2 OR PSEL0 ICK2 OR PB0 ILD2 OR PIDS DI2 OR PB1 IBF2 OR PIBF DOEN2 OR PB2 SADD2 OR PB3 IOBIT 3 0 OR PB 7 4 CKI CKI2 CKO RSTB STOP TRAP INT 1 0 IACK DI1 ICK1 ILD1 IBF1 DO1 OCK1 OLD1 OBE1...

Page 34: ...7 4 DO2 OR PSEL1 OLD2 OR PODS OCK2 OR PSEL2 OBE2 OR POBE SYNC2 OR PSEL0 ICK2 OR PB0 ILD2 OR PIDS DI2 OR PB1 IBF2 OR PIBF DOEN2 OR PB2 SADD2 OR PB3 IOBIT 3 0 OR PB 7 4 CKI CKI2 CKO RSTB STOP TRAP INT...

Page 35: ...OBIT 7 4 DO2 OR PSEL1 OLD2 OR PODS OCK2 OR PSEL2 OBE2 OR POBE SYNC2 OR PSEL0 ICK2 OR PB0 ILD2 OR PIDS DI2 OR PB1 IBF2 OR PIBF DOEN2 OR PB2 SADD2 OR PB3 IOBIT 3 0 OR PB 7 4 CKI CKI2 CKO RSTB STOP TRAP...

Page 36: ...I O VEC 3 0 OR IOBIT 7 4 DO2 OR PSTAT OLD2 OR PODS OCK2 OR PCSN OBE2 OR POBE SYNC2 OR PBSEL ICK2 OR PB0 ILD2 OR PIDS DI2 OR PB1 IBF2 OR PIBF DOEN2 OR PB2 SADD2 OR PB3 IOBIT 3 0 OR PB 7 4 CKI CKI2 CKO...

Page 37: ...O VEC 3 0 OR IOBIT 7 4 DO2 OR PSTAT OLD2 OR PODS OCK2 OR PCSN OBE2 OR POBE SYNC2 OR PBSEL ICK2 OR PB0 ILD2 OR PIDS DI2 OR PB1 IBF2 OR PIBF DOEN2 OR PB2 SADD2 OR PB3 IOBIT 3 0 OR PB 7 4 CKI CKI2 CKO RS...

Page 38: ...Configuration Register JTAG Standardized Test Port Defined in IEEE P1149 1 jtag 16 bit Serial Parallel Register pdx0 pdx7 IN Parallel I O Data Transmit Input Registers 0 7 pdx0 pdx7 OUT Parallel I O...

Page 39: ...me division Multiplex Signal Control Registers TIMER Programmable Timer timer0 Time Running Count Register timerc Timer Control Register TRACE Program Discontinuity XAB Program Space Address Bus XDB P...

Page 40: ...ternal ROM internal dual port RAM or external ROM can be addressed There are 2 16 65 536 addresses in each of the two memory spaces the total address space for each is divided into seg ments and each...

Page 41: ...nitiated to carry out the transfer The data transfer is performed first It is important to note that the selection of physical memory within a memory space is automatic because it only depends on choi...

Page 42: ...nternal Pipeline Instruction Cycle CKO Level XAB XDB AAU DECODE DAU DECODE YAB YDB 1 1 xaddr1 instr0 instr 1 yaddr 1 1 0 instr0 instr 1 data 2 2 1 xaddr2 instr1 instr0 yaddr0 2 0 instr1 instr0 data 1...

Page 43: ...data0 4 1 xaddr3 coeff instr1 yaddr1w data1w 4 0 instr2 instr1 data1r 5 1 xaddr4 instr3 instr2 yaddr2 Instruction Cycle CKO Level Process Description 1 1 The program counter PC places xaddr1 on the ad...

Page 44: ...point arithmetic and is usable as a multiply accumulate or ALU structure The DAU multiplier and adder operate in parallel requiring together one instruction cycle for their execution Microprocessor l...

Page 45: ...or deselects clearing of the lower 16 bit word of the y register and accumulators when the upper word is written It selects or deselects saturation on overflow for the accumulators It selects one of...

Page 46: ...device The cache can store up to 15 instructions at a time and can repeatedly cycle through those instructions up to 127 times without using user defined loop test and conditional branch instructions...

Page 47: ...e the dual port RAM can be downloaded through the JTAG port This download capability is also useful for self test 2 4 External Memory Interface EMI The DSP1611 17 18 27 28 29 provides a 16 bit externa...

Page 48: ...owing barrel shift operations are available arithmetic or logical shifts and left or right shifts The shift amount is from immediate data in the second word of the instruction from data in ar 0 3 or f...

Page 49: ...to accept data on an inter rupt without disrupting its normal operation In addition there are two registers used to control and monitor the PIO s operation the parallel I O control pioc register and...

Page 50: ...If data is serially shifted into the JTAG scan register it can be used to replace the real chip inputs and outputs Alternatively the real chip data on the pins can be parallel loaded into the scan reg...

Page 51: ...d DSP1611 17 18 27 28 29 supplements 2 13 Clock Synthesis DSP1627 28 29 Only The DSP1627 28 29 includes an on chip clock synthesizer that can be used to generate the system clock for the DSP The clock...

Page 52: ...Chapter 3 Software Architecture...

Page 53: ...of Interrupts 3 31 3 4 4 Interrupt Operation 3 32 3 4 5 Trap Description 3 38 3 4 6 Powerdown with the AWAIT State 3 40 3 4 7 Interrupts in DSP16A Compatible Mode DSP1617 Only 3 42 3 4 8 Timing Exampl...

Page 54: ...or the functional operators Control and status used for setting different configurations of the machine control or indicating the configura tion of the machine status Addressing used for storing infor...

Page 55: ...2 ar3 Auxiliary BMU registers data BMU auc Arithmetic unit control c s DAU c0 c1 c2 Counters data DAU cbit Control register for BIO c s data BIO cloop Cache loop count data Cache i Pointer postincreme...

Page 56: ...dress address YAAU saddx 1 2 Multiprocessor protocol register address data SIO sbit Status register for BIO c s data BIO sdx 1 2 SIO 16 bit I O registers data SIO sioc 1 2 SIO control registers c s SI...

Page 57: ...17 18 27 28 29 ioc mwait jtag JTAG BIO BMU DAU PIO CACHE CONTROL YAAU XAAU inc ins cloop alf pdx 0 7 IN pioc x y p a0 a1 auc psw c0 c1 c2 SIO sdx saddx srta tdms sioc TIMER timerc pdx 0 7 OUT CONTROL...

Page 58: ...isters address HDS BYPASS Bypass the boundary scan register 1 bit data JTAG ID Identification register 32 bits data JTAG ISR Input shift register data SIO JCON JTAG configuration register 17 bits c s...

Page 59: ...000000 psw 00 ar0 pt ar1 r0 ar2 r1 ar3 r2 auc 0000000000000000 r3 c0 rb 0000000000000000 c1 re 0000000000000000 c2 saddx cbit saddx2 cloop 000000000 sbit 00000000PPPPPPPP i sdx inc 0000000000000000 sd...

Page 60: ...domly set or a cleared bit The bit is randomly set with probability of 0 5 The random bit is generated by a 10 stage pseudorandom sequence generator PSG that is updated after either a heads or tails t...

Page 61: ...nd as long as the banks accessed are different simultaneous data and instruction accesses can be made If the same bank is accessed from both memory spaces simultaneously an extra instruction cycle one...

Page 62: ...C00 0x0FFF RAM4 RAM4 RAM4 RAM4 RAM4 RAM4 RAM4 4096 0x1000 0x13FF RAM5 Reserved RAM5 RAM5 RAM5 RAM5 RAM5 5120 0x1400 0x17FF RAM6 RAM6 RAM6 RAM6 RAM6 RAM6 6144 0x1800 0x1BFF RAM7 Reserved RAM7 RAM7 RAM7...

Page 63: ...memories is automatic corresponding to the address in the XAAU and the memory map selected Each physical memory device has a corresponding address space but unlike the YAAU the relationship between th...

Page 64: ...e user selected map is restored at the end of the HDS trap service routine LOWPR is an alf register bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1...

Page 65: ...12K 16384 0x4000 0x5FFF IROM 24K EROM 48K 24576 0x6000 0x7FFF Reserved 8K 32768 0x8000 0x9FFF EROM 16K 40960 0xA000 0xBFFF Reserved 8K 49152 0xC000 0xCFFF RAM 1 4 4K RAM 1 4 4K EROM 16K 53248 65535 0x...

Page 66: ...S trap service routine LOWPR is an alf register bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if...

Page 67: ...gies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable option is selected MAP4 EXM 1 LOWPR 1 0 0x000...

Page 68: ...Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable option is selected MAP4 EXM 1...

Page 69: ...an alf register bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable optio...

Page 70: ...rvice routine LOWPR is an alf register bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure m...

Page 71: ...ter bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable option is selected...

Page 72: ...rvice routine LOWPR is an alf register bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure m...

Page 73: ...RAM depending on the memory map in force Table 3 18 shows the vectors assigned to interrupts in the X memory space Table 3 18 Interrupts in X Memory Space Vector Description Vector Address Reset vecto...

Page 74: ...0 determine the bit alignment of the data in p with respect to the data in the accumulators The connection of the data bus to the p register the RAM the accumulators and the remaining registers in the...

Page 75: ...Value Description RAND 0 1 Pseudorandom sequence generator PSG is reset by writing the pi register only outside an interrupt service routine PSG never reset by writing the pi register X Y 0 1 Normal o...

Page 76: ...the p register is not shifted with respect to the bits in the accumulator before product bits 31 0 are transferred into bits 31 0 of the accumulator In the accumulator the sign bit from the p registe...

Page 77: ...e right with respect to the bits in the accu mulator as product bits 31 2 are transferred into bits 29 0 of the accumulator Bits p 1 0 are lost The sign of p bit 31 is extended by 6 bits into bits 35...

Page 78: ...e x register are in Q14 for mat 2 magnitude bits 14 fractional bits and state variables in the y register are 16 bit integers If the p register is not shifted prior to accumulation the accumulated res...

Page 79: ...in the x register are in Q15 format 1 magnitude bit 15 fractional bits and state variables in the y register are 16 bit integers If the p register is not shifted prior to accumulation the accumulated...

Page 80: ...al of 13 interrupts and two traps see Table 3 20 Interrupt service routines cannot be interrupted Branch instructions conditional branch instructions postdecre ments of Y address registers and cache l...

Page 81: ...ontinued 3 4 1 Introduction continued Figure 3 8 is a functional block diagram of the interrupt hardware 5 4115b Figure 3 8 Interrupt Operation JINT OBE2 IBF2 TIME INT 1 0 OFF CHIP PIDS PIBF PODS POBE...

Page 82: ...can be enabled from inc POBE Parallel output buffer empty flag indicates that the parallel output data register has been read by an external device POBE can be enabled from inc INT 1 0 Interrupt by an...

Page 83: ...1998 3 30 DRAFTCOPY Lucent Technologies Inc 3 4 Interrupts continued 3 4 2 Interrupt Sources continued 5 4146 Figure 3 9 DSP16A Compatible Interrupts DSP1617 Only PIDS PODS OBE IBF INTERRUPT PROCESSI...

Page 84: ...multiplexed with pins IOBIT 7 4 Bit 12 of the ioc register must be cleared to enable VEC 3 0 Issued by Cleared By No interrupt 0x0 Software interrupt 0x2 1 lowest 0x1 icall The icall instruction is r...

Page 85: ...decodes the vector address of the pending interrupt In the following cycle during time frame C the interrupt is acknowledged on the VEC and IACK pins The PC register is loaded with the next instructio...

Page 86: ...pin is synchronized and latched in interrupt pending latch B Executing an interruptible instruction C Branch to interrupt routine D Start executing instructions in interrupt service routine E ireturn...

Page 87: ...x clears PODS POBE Reading sdx clears IBF writing to sdx clears OBE see Section 8 3 Interrupts and the PIO for more detail The JTAG interrupt is cleared by reading the jtag register If the vec tored i...

Page 88: ...The reference is the time at which instruction words are fetched on the XDB program data bus 5 4117 Figure 3 11 Interrupt Disable Latency The interrupt pins are latched on the falling edge of CKO The...

Page 89: ...rrupt requests internal or external occur at the same time or pending interrupts are enabled at the same time and the device is not servicing any of the pending requests all the interrupts will be ser...

Page 90: ...e interrupt is asserted again while the first interrupt request is being serviced 5 4118 CKO is a zero wait stated clock Notes A INT1 pin is synchronized and latched in interrupt pending latch B Execu...

Page 91: ...nts the long interrupt response time is too slow to gain control of the pro cessor and remove the exception condition Therefore programming techniques such as breaking long cache loops into several sh...

Page 92: ...TRAP pin is synchronized and latched in interrupt pending latch B A constant two cycle delay to allow a two cycle instruction to complete before entering into the trap service routine C Branch to trap...

Page 93: ...WAIT bit is set one more instruction cycle is executed before entering the standby powerdown mode After an interrupt request wakes up the processor one more instruction cycle is executed before being...

Page 94: ...COPY 3 41 3 4 Interrupts continued 3 4 6 Powerdown with the AWAIT State continued Code Example for Sleep Mode assuming execution from internal RAM sleep alf 0x8000 set bit 15 of alf register nop one m...

Page 95: ...ad of the falling edge of CKO as in DSP16A However ORing VEC0 and VEC1 in the DSP16A compatible mode generates a signal equivalent to the DSP16A IACK signal The software interrupt icall branching to l...

Page 96: ...e the DSP16A there is no need to hold the INT0 signal until the next rising edge of IACK If the IBF interrupt is recognized while servicing the external interrupt it is ser viced at the next interrupt...

Page 97: ...its in pioc set INT0 in the pioc register is cleared when IACK goes low IBF is cleared upon reading of sdx Case 2 INT0 is asserted one clock cycle after IBF and latched internally at point B Interrupt...

Page 98: ...nt A and IBF at point B Interrupt is caused by INT0 with both status bits in pioc set INT0 latch is negated when IACK goes high Case 2 IBF is asserted two clock cycles after INT0 and latched internall...

Page 99: ...nal is negated at point B and asserted again at point C Because the previous INT0 is still pending the new INT0 must be asserted until the second rising edge of IACK Case 2 INT0 signal is negated at p...

Page 100: ...ternal processor clocks and CKO Setting the appropriate bits in the pllc control register see Table 3 26 will enable the clock syn thesizer to become the clock source The powerc register which is disc...

Page 101: ...e at least twice fCKI The coding of the Mbits and Nbits is described as follows Mbits M 2 if N 1 Nbits 0x7 else Nbits N 2 where N ranges from 1 to 8 and M ranges from 2 to 20 Program the loop filter b...

Page 102: ...east 2x fCKI Change the bits in the pllc register only if the PLL is not providing the internal clock source To select the PLL as the internal clock 1 Program all bits in the pllc register to the desi...

Page 103: ...flag assertion pllc 0xE912 Select high speed PLL clock 2 nop Switch to PLL latency goto start User s code now running at 50 MHz pllwait if lock return goto pllwait Section 3 6 6 Power Management Exam...

Page 104: ...3 27 PLL Electrical Specifications and pllc Register Settings M VDD pllc13 ICP pllc12 SEL5V pllc 11 8 LF 3 0 Typical Lock in Time s See Note 2 23 24 2 7 V 3 6 V 1 0 1011 30 21 22 2 7 V 3 6 V 1 0 1010...

Page 105: ...It is recom mended that if INT0EN is to be used the INT0 interrupt be disabled in the inc register so that an unintended interrupt does not occur After the program resumes the INT0 interrupt in the i...

Page 106: ...units Table 3 28 powerc Fields DSP1617 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 0 Field XTLOFF SLOWCKI NOCK INTOEN rsvd INT1EN rsvd SIO1DIS SIO2DIS PIODIS TIMERDIS rsvd Table 3 29 powerc Fields DSP1611 DSP...

Page 107: ...nternal processor clock The switching of the multiplexers and the synchronous gate is designed to be clean in the sense that no partial clocks occur If the deep sleep state is entered with the ring os...

Page 108: ...he switching of the multiplexers and the synchronous gate is designed to be clean in the sense that no partial clocks occur If the deep sleep state is entered with the ring oscillator selected the int...

Page 109: ...CKI bit of powerc 3 6 4 AWAIT Bit of the alf Register Setting the AWAIT bit of the alf register causes the processor to go into the standard sleep state or power saving standby mode Operation of the A...

Page 110: ...r start up interval to be satisfied A similar interval is required for the small signal input circuit to reach its dc operating point A minimum reset pulse of 20 ms is adequate The falling edge of the...

Page 111: ...nop Only sleep power consumed here until interrupt wakes up the device next User code executes here powerc 0x0 Turn peripheral units back on Sleep with Slow Internal Clock1 In this case the ring oscil...

Page 112: ...small signal is stable next powerc 0x00F0 Select high speed clock 2 nop Wait for it to take effect powerc 0x0000 Turn peripheral units back on Software Stop In this case all internal clocking is disab...

Page 113: ...user chooses 6 Whether or not the PLL is enabled Power Management Examples with the PLL DSP1627 28 29 Only The following examples show the more significant options for reducing power dissipation if op...

Page 114: ...ternal Clock and Crystal Oscillator Small Signal Disabled PLL Disabled If the target device contains the crystal oscillator or the small signal clock option the clock input circuitry can be powered do...

Page 115: ...cks stop Minimum switching power consumed here 3 nop Some nops will be needed INT0 pin clears NOCK field clocking resumes cont powerc 0x4000 INTOEN cleared and XTLOFF cleared if applicable call xtlwai...

Page 116: ...Chapter 4 Instruction Set...

Page 117: ...4 3 4 3 2 Compound Addressing 4 5 4 3 3 Direct Data Addressing 4 7 4 4 Processor Flags 4 9 4 5 Instruction Set 4 11 4 5 1 Control Instructions 4 12 4 5 2 Cache Instructions 4 14 4 5 3 Data Move Instru...

Page 118: ...basis of the state of internal flags Multiply ALU instructions are the primary instructions for signal processing programs that perform multiply accu mulate logical and other ALU functions They also...

Page 119: ...f CON F2 F3 ALU instructions F4 BMU instructions The valid instruction groups for the DSP device are represented in Tables 4 1 to 4 17 The items in these tables that are written in lower case letters...

Page 120: ...ound addressing one addressing reg ister points to a memory location or locations for a read followed by a write The instruction also specifies a register for the swap and the addressing register can...

Page 121: ...M j The j following the address register indicates a postincrement of the address register This example means the data pointed to by the address in the register and add the value of register j to the...

Page 122: ...mp used in the descriptions is a hypothetical register used for illustration only Note that postincrementation can occur after either Step 2 or Step 3 in Table 4 1 Note M can be 0 1 2 or 3 R can be on...

Page 123: ...s pictorially 5 4148 j or k can be positive or negative Figure 4 1 Compound Addressing rMzp R INITIAL ADDRESS IN rM FINAL ADDRESS IN rM Y MEMORY Y ADDRESSING REGISTER rMpz R INITIAL ADDRESS IN rM FINA...

Page 124: ...nts of rb If the contents of the address register are equal to the contents of re during the write cycle and the rMzp mode is specified rM is loaded with the contents of rb Two of the compound address...

Page 125: ...1 bits of 0x1232 into ybase as follows Place 0001 0010 001 into the upper 11 bits of ybase 0x15 a0 Offset 0x15 Store 1 0101 into lower 5 bits of ybase Address in ybase is 0x1215 demonstrated below 000...

Page 126: ...t set flags Four of the basic processor flags are defined below They can be set by either ALU or BMU operations These flags and their meanings are given below LMI Logical Minus A logical minus is dete...

Page 127: ...est The pseudorandom sequence can be reset by writing any value to the pi register except during an interrupt service rou tine While in an interrupt service routine writing to the pi register will upd...

Page 128: ...FSET DR push rM R R pop rM Special Function if CON F2 ifc CON F2 Multiply ALU F1 Y F1 Y a0 l F1 Y a1 l F1 x Y F1 y l Y F1 y Y F1 y a0 F1 y a1 F1 aT l Y F1 Y y l F1 Z y l F1 Z aT l F1 Z y F3 ALU aD aS...

Page 129: ...Instructions Control instructions cannot be used in the cache Table 4 5 lists replacements for the upper case fields shown in this table Control Instruction Equivalent Instruction if applicable Encod...

Page 130: ...ows branches to any location in the 64 Kword program space The goto pt instruction does not affect the program return register call pt The call pt instruction moves the contents of the PC into the pr...

Page 131: ...value in cloop decrements every cache loop and is decremented to zero at the end of the do or redo instruction The cloop register will also contain the cache count from a do K or redo K instruction K...

Page 132: ...ove instructions perform three basic operations moving immediate data to a register moving data between a register and an accumulator and moving data between a register and Y memory space All data mov...

Page 133: ...egister unsigned XAAU increment register signed psw Processor status word sioc sdx tdms srta Serial I O control register Serial I O data register Serial I O tdms control register Serial receive transm...

Page 134: ...rb re j k Subset of registers for short immediate aS aT a0 a1 High half of accumulator bits 31 16 aSl aTl a0l a1l Low half of accumulator bits 15 0 Y rM rM rM rM j Same as in multiply ALU instruction...

Page 135: ...of the specified accumulator aS into the specified destination register R If saturation on overflow is enabled according to the SAT field of the auc register the transferred accumulator value is limi...

Page 136: ...3 The result of the most recent accumulator or BMU operation prior to the special function instruction establishes the state of the flags for the conditions associated with logical or mathematical fun...

Page 137: ...mulator aDh aSh 1 Increment high half of accumulator lower half cleared aD aS 1 Increment accumulator aD y aD p 32 bit transfer sign extend into guard bits 35 32 aD aS 1 aD aS 4 aD aS 8 aD aS 16 Arith...

Page 138: ...aD aS 8 The contents of the source accumulator aS are shifted 8 bits left and the result is placed in the destination accumulator aD The sign bit is extended from the new bit 31 The least significant...

Page 139: ...assembled by using statements from the function column that include the multiplication of the data in x and y bits 31 16 In a full multiply accumulate instruction the x and y registers are loaded wit...

Page 140: ...struction is either nop or a single semicolon and is assembled as r0 Note that the function statements and transfer statements in Table 4 12 are chosen independently Any function statement can be comb...

Page 141: ...0 A table of values pointed to by r1 can thus be squared in a pipeline with one instruction cycle per each value The following sample program demonstrates the use of the single cycle square a0 a0 a0 c...

Page 142: ...ed from the contents of the source accumulator aS and the result is placed in the destination accumulator aD The bit alignment between p and aS is a func tion of the ALIGN field of the auc register Th...

Page 143: ...loaded into the high half bits 31 16 of the y register The data from the specified X source is loaded into the x register If clearing of yl is enabled by using the CLR field of the auc register yl is...

Page 144: ...a from the specified Z source is loaded into the low half bits 15 0 of the y register and the old data of the low half of the y register is loaded into the Z destination Data in the high half of the y...

Page 145: ...umulator or the y regis ter Only one of the four possible postmodification conditions is shown rMpz The others are the same as in Sec tion 4 3 2 Compound Addressing Z aTl rMpz aTl INITIAL ADDRESS IN r...

Page 146: ...d are two cycle If PC points to external memory add programmed wait states Table 4 15 F3 ALU Instructions Instruction Description aD aS OP aT Perform an operation between two accumulators and place th...

Page 147: ...four 16 bit auxiliary registers ar 0 3 that contain input or output operands The BMU is fully described in Chapter 13 Bit Manipulation Unit BMU Instructions aD a SHIFT aS aD aS SHIFT arM aD aS SHIFT I...

Page 148: ...e is negative the direction of the shift is reversed For these instructions flags are set based on the value written to aD For left shifts the LLV flag is set if any signif icant bits are lost from th...

Page 149: ...laced in aD Flags are set based on the value written to aD Bit Field Extraction and Insertion aD extracts aS arM aD extractz aS arM An arbitrary selected sequence of contiguous bits in the 36 bit aS r...

Page 150: ...original location to a new location determined by the OFFSET The remaining bits are filled with the corresponding bits from the other accumulator For example the instruction a0 insert a0 ar1 moves a b...

Page 151: ...t operation in the BMU and can be used by the conditional instructions just like DAU flags LMI Logical Minus Bit 35 of the destination accumulator after the shift If bit 35 1 sign is negative and LMI...

Page 152: ...in the auc register The type of instruction is critical if conditional testing based on the results of the instruction execution is performed The DSP1600 flags are affected by multiply ALU instruction...

Page 153: ...us instructions that might need a mnemonic Table 4 18 Summary of Ambiguous DSP1600 Commands Requiring a Mnemonic j LABEL1 k LABEL1 rb LABEL1 re LABEL1 rM LABEL1 a1 a0 a0 a1 a0 rM a0l rM a1 rM a1l rM y...

Page 154: ...Chapter 5 Core Architecture...

Page 155: ...dom Sequence Generator PSG 5 7 5 1 7 Control Registers 5 9 5 2 X Address Arithmetic Unit XAAU 5 11 5 2 1 Inputs and Outputs 5 11 5 2 2 X Memory Space Segment Selection 5 11 5 2 3 Register Descriptions...

Page 156: ...two 36 bit accumulators a0 and a1 The DAU performs two s complement fixed point arithmetic and has a complete set of multiply accumulate and ALU instructions The DAU multiplier and adder operate in p...

Page 157: ...means either If auc bit 6 0 yl is cleared with a write to y If auc bit 6 1 yl is not cleared with a write to y Writing yl does not affect y The 32 bit p register provides a 36 bit input for ALU functi...

Page 158: ...auc 3 1 saturation is disabled for a1 If auc 2 0 saturation is enabled for a0 If auc 2 1 saturation is disabled for a0 The overflow condition exists if the value in the 36 bit accumulator is too larg...

Page 159: ...n 4 5 1 by referencing the conditional mnemonics described in Table 5 1 The DAU interprets 8 bit numbers stored in c0 c2 as two s complement numbers The most negative number maximum count stored is 27...

Page 160: ...c1 1 4 initialize c1 to 1 4 3 innerloop instruction do operations in innerloop if c1lt goto innerloop repeat innerloop for c1 if c1 0 instruction go on more outerloop ops if c0lt goto outerloop repeat...

Page 161: ...enting counter Increments by one whenever an instruction of the form if c0ge Instruction or if c0lt Instruction executes c1 General purpose incrementing counter Increments by one whenever an instructi...

Page 162: ...If the heads or tails flags are tested within a subroutine and different arrays of random sequences are desired each time the subroutine is called the PSG should be reset only once in the main program...

Page 163: ...m Sequence Generator PSG continued 5 4157 The PSG clock is pulsed whenever a heads or tails condition exists The PSG is set to all ones whenever the pi register is written outside of an interrupt serv...

Page 164: ...w This can happen if any significant bits are lost after adding subtracting or shifting overflow numbers The psw register contains the status of two additional DAU flags LEQ and LMI The LEQ psw 14 bit...

Page 165: ...Flags X a1 V a1 35 32 a0 V a0 35 32 Bit s Field Value W indicates that the bit can be read or written Result Description 15 12 DAU Flags All DAU flags can be read from the psw register The DAU flags a...

Page 166: ...ed in Section 3 2 Memory Space and Addressing 5 4158 Figure 5 5 XAAU X Address Arithmetic Unit 5 2 1 Inputs and Outputs The outputs of the XAAU are the instruction coefficient address bus XAB and the...

Page 167: ...ice routine ISR this shadowing is disabled and pi holds the last value of PC actually the address after the address of the last instruction executed before the interrupt was taken The return from inte...

Page 168: ...e to the user and can be read or written under program control 5 4159 Figure 5 6 YAAU Y Address Arithmetic Unit 5 3 1 Inputs and Outputs The major output of the YAAU is the YAB that provides addresses...

Page 169: ...selecting one of 16 registers e g r0 or a0 as the source or destination for the data move and 5 bits that form the offset part of the address see Section 4 3 2 Compound Addressing and Section 4 5 3 D...

Page 170: ...ddressing is executed see Section 4 3 3 Direct Data Addressing the instruction contains 4 bits selecting one of 16 registers e g r0 or a0 as the source or destination for the data move and 5 bits that...

Page 171: ...gister such as r1 contains an address that increments as the pointer advances through the memory If the pointer register address equals the address in re1 and the current instruction calls for a posti...

Page 172: ...and provides decoding for registers outside of the DSP1600 core It stretches the processor cycle if wait states are required wait states can be programmed for external memory access via the mwait reg...

Page 173: ...iterations K for a do or redo can be set at run time by first moving the number of iterations into the cloop register 7 bits unsigned and then issuing the do cloop or redo cloop instruction The cloop...

Page 174: ...ins alf and mwait registers inc ins and alf are described in Tables 5 9 through 5 11 For further information refer to the sections listed in Table 5 6 Table 5 6 Control and Status Descriptions Regist...

Page 175: ...eserved ebusy nmns1 mns1 evenp oddp somef somet allf allt Bit Flag Use 15 AWAIT Set to enter power saving standby mode or standard sleep mode 14 LOWPR Memory map selection 13 9 Reserved 8 ebusy ECCP b...

Page 176: ...Chapter 6 External Memory Interface...

Page 177: ...4 Timing Examples 6 17 6 4 1 CKO Timing 6 17 6 4 2 Write Read Read W 0 6 18 6 4 3 Read Write Write W 0 6 19 6 4 4 Read Write W 0 Compound Address 6 20 6 4 5 Read W 1 Read W 2 6 21 6 4 6 Write W 1 6 22...

Page 178: ...not accessed and wait states allow the use of slow low power memories 6 1 EMI Function DSEL not available in the DSP1627 28 29 5 4126 b Figure 6 1 External Memory Interface Figure 6 1 shows the block...

Page 179: ...es Outputs from the DSP The four leads EROM ERAMHI IO and ERAMLO are used to select one of the four external memory segments If an enable is low the segment associated with that enable is selected Add...

Page 180: ...efficient Memory Map X Memory Space Decimal Address Address in pc pt pi pr MAP1 EXM 0 LOWPR 0 MAP1 is set automatically during an HDS trap The user selected map is restored at the end of the HDS trap...

Page 181: ...FF IROM 24K EROM 48K 24576 0x6000 0x7FFF Reserved 8K 32768 0x8000 0x9FFF EROM 16K 40960 0xA000 0xBFFF Reserved 8K 49152 0xC000 0xCFFF RAM 1 4 4K RAM 1 4 4K EROM 16K 53248 65535 0xD000 0xFFFF Reserved...

Page 182: ...LOWPR is an alf register bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if the secure mask progr...

Page 183: ...m tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable option is selected MAP4 EXM 1 LOWPR 1 0 0x0000 0x0FFF IROM 36K EROM...

Page 184: ...velopment system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable option is selected MAP4 EXM 1 LOWPR 1 0 0x0000 0x0FF...

Page 185: ...he Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable option is selected MAP4 EXM...

Page 186: ...an alf register bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable optio...

Page 187: ...chnologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable option is selected MAP4 EXM 1 LOWPR 1 0...

Page 188: ...s an alf register bit The Lucent Technologies development system tools can independently set the memory map MAP2 EXM 1 LOWPR 0 MAP3 EXM 0 LOWPR 1 MAP3 is not available if secure mask programmable opti...

Page 189: ...ess Hexadecimal Address in r0 r1 r2 r3 DSP1611 DSP1617 1618 DSP1627 DSP1628 x08 DSP1628 x16 DSP1629 x10 DSP1629 x16 0 0x0000 0x03FF RAM1 RAM1 RAM1 RAM1 RAM1 RAM1 RAM1 1024 0x0400 0x07FF RAM2 RAM2 RAM2...

Page 190: ...f the enable can be delayed to avoid a situation in which two devices can drive the data bus simultaneously Logic sense of DSEL Bit 6 in the ioc register selects the logic sense of the DSEL1 output If...

Page 191: ...in The flexibility of the wait states in the DSP allows a wide range of memory speeds to be used 5 4161 Figure 6 2 EMI Example Table 6 14 CKO Options CKO2 CKO1 CKO0 CKO Output Description 1X CKI 2X CK...

Page 192: ...e of instructions in a pro gram a read and a write cycle definition can be different For example all write instructions take two instruction cycles but the corresponding enable low time is one instruc...

Page 193: ...ry enables goes low or the leading edge can be delayed one half a CKO period by programming a bit in the ioc Address bus becomes valid RWN goes low Midcycle CKO goes low for an odd number of wait stat...

Page 194: ...rammable Features The free running CKO is the frequency of CKI divided by two 2x input clock option It will have a 50 duty cycle within the accuracy of the rise and fall times If wait states occur the...

Page 195: ...because a read cycle follows immediately The external memory responds to the request for a read by placing data on the DB sometime before the end of the read cycle and the data is latched into the DSP...

Page 196: ...during each cycle and remains valid until the next cycle starts The data bus DB is driven by data from the external memory during the read cycle During the first half of the write cycle the DSP 3 sta...

Page 197: ...es to the write address at the beginning of the write cycle At some time in the read cycle the data bus DB is driven by the external memory to valid data that is latched into the DSP at the end of the...

Page 198: ...the external memory will respond by 3 stating the data bus The EROM address remains valid until the next valid address is required Sometime later one CKO period in this example the next read cycle sta...

Page 199: ...address is placed on the address bus the data bus is 3 stated by the DSP and RWN goes low Halfway through the write cycle in this case one CKO period later the data is placed on the data bus by the D...

Page 200: ...tion coefficient memory had not yet released the bus a problem could be caused by both driving the bus At the least high currents would result To avoid this condition a bit is programmed in the ioc re...

Page 201: ...f the data bus The delay is selected by programming a bit in the ioc register see Section 6 2 Programmable Features Another point of this example is to show that the DSP does not provide extra hold ti...

Page 202: ...it register can be initialized with all the external memory segments having 15 wait states by setting the INT1 external pin low As the program executes it can reset the wait states to a more appro pri...

Page 203: ...ion cycles number of cycles normal operation XWS YWS 1 where XWS X programmed wait states mwait register YWS Y programmed wait states mwait register The sample code segment illustrates the problem rse...

Page 204: ...tion cycles used by the memory sequencer DSP1610 DSP1616 Users If on the DSP1610 or the DSP1616 an X and Y access to external memory is specified in the same instruction an interrupt called EMUXBOTH o...

Page 205: ...384 to 65535 can be modified in this manner Locations 0 to 16383 in EROM space are still inaccessible Setting the EXTROM bit in conjunction with the WEROM bit in the ioc causes the processor to force...

Page 206: ...rupt vector 0x34 pidsint Test which byte if c1lt goto byte1 byte0 Read in lower byte word Form the word a0 a0 a1 Write out to EROM r0 a01 Reset byte counter c1 1 Read the pointer a1 r0 XOR with zero a...

Page 207: ...t the page counter r1 0x1 Set the byte counter c1 1 Wait for 64 Kwords to be downloaded into EROM space wait nop goto wait Stop if done stop goto stop The counter c1 is used as a byte marker because o...

Page 208: ...Chapter 7 Serial I O...

Page 209: ...ial I O Pin Descriptions 7 12 7 4 Codec Interface 7 13 7 5 Serial I O Programming Example 7 14 7 5 1 Program Segment 7 14 7 6 Multiprocessor Mode Description 7 15 7 6 1 Multiprocessor Mode Overview 7...

Page 210: ...te addressing other DSP devices in multiprocessor mode The second SIO unit SIO2 is functionally identical to SIO1 The SIO2 pins are multiplexed with the PIO pins for the DSP1617 and with the PHIF pins...

Page 211: ...oc or tdms register having a value of zero Five signals can be individually programmed to be either inputs or outputs passive or active ICK OCK ILD OLD and SYNC ICK and OCK are the input and output po...

Page 212: ...CK and OCK and assumes that the CKO 2 mode has been selected All active mode transitions occur on the rising edge of CKO and all active mode outputs are square waves 50 duty cycle SYNC transi tions al...

Page 213: ...field if the input shift register isr fills this data is transferred to the input buffer register sdx IN At this time the input buffer full IBF flag and signal are also asserted indicating that the b...

Page 214: ...s an interrupting condition by setting the IBF interrupt enable bit in the inc register bit 0 for vectored interrupts These bits are cleared when sdx is read IBF is cleared on reset For the DSP1617 on...

Page 215: ...action This procedure causes the contents of the output buffer register sdx out to be transferred to the output shift OSR register the OBE flag and signal to be set indi cating the need for more data...

Page 216: ...the LD bit of the sioc register bit 9 must be set high to synchronize SADD with DO and the MODE bit of the tdms register bit 8 must be set low to turn off multiprocessor mode Under these conditions a...

Page 217: ...8 bit word size selected via the sioc OLEN field bit 1 The overall pipelining between successive words is the same as for 16 bit mode Because the active mode ILD and OLD generators can only be set to...

Page 218: ...6 5 4 3 2 1 0 Field LD CLK MSB OLD ILD OCK ICK OLEN ILEN Table 7 2 Serial I O Control sioc Register DSP1627 28 29 Only Bit 10 9 8 7 6 5 4 3 2 1 0 Field DODLY LD CLK MSB OLD ILD OCK ICK OLEN ILEN Table...

Page 219: ...read or write occurs the MSB field can be switched immediately before after or both before and after an sdx read or write If this technique is used in other than an interrupt ser vice routine care sh...

Page 220: ...to sdx the output buffer poll to see when the output buffer empties poll to see if the input buffer is full and read from sdx The input buffer full flag or the output buffer empty flag can also be us...

Page 221: ...gister MODE field set DOEN indicates a valid time slot for a serial output and is bidirectional OCK I O Output Clock Clock for serial output data Corresponding to the sioc register OCK field in active...

Page 222: ...ample OCK of the DSP is active and ICK ILD and OLD are passive The codec is in the nonmultiprocessor mode although it can be used in the multiprocessor mode In the second example both input and output...

Page 223: ...d and the process repeats 7 5 1 Program Segment Programming Examples Ping pong I O routine for DSP1617 goto start 0x2c intrpt r0 sdx ireturn start auc 0x0 pioc 0x200 interrupt on IBF sioc 0x0 passive...

Page 224: ...e system The SIO ports SIO1 and SIO2 can be individually configured for multipro cessor mode Figure 7 11 shows how the DSPs are connected together over a four wire bus All of the DSPs have access to t...

Page 225: ...mitted serially on ADD at the same time as the first 8 bits of the data Figure 7 12 illustrates this concept 5 4182 Figure 7 12 Destination Address Communication The receiving DSP might need to know w...

Page 226: ...e connected together to form a four wire bus as shown in Figure 7 14 The DI and DO pins form a single wire data bus referred to as DATA ICK and OCK form a clock line referred to as CK SADD forms a sin...

Page 227: ...in Figure 7 15 The ILD output clocks with every time slot to read in each word of address and data and the OLD output clocks only on those time slots during which the DSP in question actually drives...

Page 228: ...7 16 Multiprocessor Mode Output Timing Whenever a DSP drives the bus in some time slot the address of the destination DSP s is sent out on the ADD line concurrent with the transmission of the first 8...

Page 229: ...he destination DSP s along with the data and can be used for any desired purpose For example the top 3 bits of the saddx value is sufficient to encode a source ID for each source DSP up to eight maxim...

Page 230: ...changed it is imperative that each processor still have its own unique time slot All new time slots are updated at the end of each time slot 0 refer to Figure 7 15 During reset the tdms register clea...

Page 231: ...t can transmit to device 3 and receive address 7 The serial data register sdx of device 7 contains the data to be transmitted During time slot 0 the data from device 7 is transmitted on the TDM channe...

Page 232: ...Figure 7 17 DSP1611 17 18 27 28 29 Multiprocessor Communications srta 0x2000 r1 sdx 7 6 5 4 3 2 1 0 0 1 2 4 3 5 6 7 TIME SLOT NUMBER tdms 0x120 srta 0x01FE sdx r1 srta 0x0200 a0 sdx srta 0x0400 a0 sdx...

Page 233: ...ly be set up to drive time slot 0 because this device will also drive SYN If SYN is to be externally generated no DSP device should ever drive time slot 0 because this would cause a conflict on the SY...

Page 234: ...errupts srta 0xNNNN set srta to desired transmit receive values and continue with program Different DSPs need to drive different time slots Each DSP can drive more than one if desired The number of no...

Page 235: ...the SIO2 that differentiate it from the SIO1 the user should refer Section 7 1 SIO Operation for the features that are the same 7 7 1 SIO2 Features The SIO2 block is identical to SIO1 from a function...

Page 236: ...input output MSB first or LSB first Both input and output data formats can be independently configured See Table 7 3 on page 9 for the values that are encoded in each field Additional programmable reg...

Page 237: ...Chapter 8 Parallel I O DSP1617 Only...

Page 238: ...nteraccess Timing 8 5 8 1 3 Passive Mode 8 6 8 1 4 Peripheral Mode Host Interface 8 9 8 2 Programmer Interface 8 14 8 2 1 pioc Register Settings 8 16 8 2 2 Latent Reads 8 17 8 2 3 Power Management 8 1...

Page 239: ...hysical PIO port there are eight logical PIO ports pdx0 through pdx7 In active mode the state of the peripheral select pins PSEL 2 0 shows which logical port is selected The data path of the PIO is co...

Page 240: ...pins PSEL 2 0 are outputs of the DSP that indicate which of the eight channels are being accessed If either input or output is passive some of these pins become inputs and serve different purposes see...

Page 241: ...s for the data has been selected One half a CKO cycle later PIDS is pulled low signaling that an external device can place data on the parallel data bus PB The duration of PIDS is configurable in the...

Page 242: ...of the pdx channels e g pdx0 r2 If an active mode output occurs PSEL 2 0 are asserted to indicate which of eight possible external devices will be the destination One half a CKO cycle later the DSP p...

Page 243: ...DSP drives PODS and PIDS and the DSP and external device alternate in driving the PB Figure 8 4 shows the timing of mixed active mode inputs and outputs See Section 8 1 1 Active Mode for specific des...

Page 244: ...t is placed in passive mode Table 8 2 shows the effects of various modes on the PSEL 2 0 bits Table 8 5 shows the complete encoding for PSEL 2 0 as outputs 000 corresponding to port pdx0 etc If passiv...

Page 245: ...O an external device must first pull the PSEL2 pin low Then the passive mode input transaction shown in Figure 8 5 can be initiated by the external device asserting PIDS It must then place data onto t...

Page 246: ...this time If the PIO s status is sought the external device should drive this input high If the contents of the pdx OUT register are sought PSEL1 should be driven low Then the passive mode output tra...

Page 247: ...and POBE are flags that indicate parallel input buffer full and parallel output buffer empty They are both active high The input flag works if PIDS is in passive mode and is cleared otherwise The outp...

Page 248: ...active mode input otherwise the input is in passive mode There is no need to present the same information about PODS because PSTAT can only be read during a pas sive mode output PIBF If set the paral...

Page 249: ...O If the flags are being monitored this can be in response to PIBF or PSEL0 going low The external device then drives PIDS low It must then place the data on the PB and leave it there until after PIDS...

Page 250: ...external device then drives PODS low If data is being requested as is the case below PSEL1 must be driven low at this time Shortly after PODS is asserted the PIO drives data onto the PB Shortly after...

Page 251: ...er Polling the PSTAT register see Figure 8 10 is identical to a passive or peripheral mode output The main differ ence is the PSEL1 pin must be held high while PODS is asserted No flags are affected P...

Page 252: ...ng the device nine PIO registers can be referenced pioc PIO control register pdx0 Logical port 0 pdx1 Logical port 1 pdx2 Logical port 2 pdx3 Logical port 3 pdx4 Logical port 4 pdx5 Logical port 5 pdx...

Page 253: ...scription IBF R IBF interrupt status bit same as bit 4 STROBE 00 01 10 11 Strobe width of PODS PIDS T T 2T 2T 3T 3T 4T 4T T 1 CKO clock period PODS 0 1 PODS is an input passive mode PODS is an output...

Page 254: ...bit 12 of the pioc register is equal to logic 0 the PODS pin is an input used by external devices to request the DSP to write Bit 11 if equal to logic 1 makes the PIDS pin an output accordingly the DS...

Page 255: ...reads the first word d0 from the parallel input register and initiates the transaction to bring the second word d1 from the external device 3 The third instruction reads the second word d1 from the p...

Page 256: ...2 Latent Reads continued 5 4196 Figure 8 11 PIO Latent Reads Hardware 5 4197 a Figure 8 12 PIO Latent Reads Timing PIO STROBES PIDS EXTERNAL DEVICE PB 8 pdx IN IDB 16 DSP1617 CKO PSEL 2 0 PIDS PB VAL...

Page 257: ...pt routine the DSP program performs I O functions The receipt of data and the conclusion of the interrupt service routine by the DSP is indicated to the external data source by the falling edge high t...

Page 258: ...DSP reading from the PIO registers to clear pioc 2 does not cause an external read transaction to take place PODS pioc 1 indicates that an external device has read from the DSP s PIO register Writing...

Page 259: ...PIDS is an output When PIDS is driven low data can be placed onto the PB bus When PIDS goes high data should be removed from the PB bus PIDS is asserted by the DSP during active mode read transaction...

Page 260: ...Section 8 2 2 Latent Reads When the PIOLB bit is set the PIO is configured for loopback the PB pins are 3 stated and an internal connec tion is made between pdx OUT and pdx IN Both PODS and PIDS are 3...

Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...

Page 262: ...Bit Read 9 3 9 1 2 Intel Mode 16 Bit Write 9 4 9 1 3 Motorola Mode 16 Bit Read 9 5 9 1 4 Motorola Mode 16 Bit Write 9 6 9 1 5 8 Bit Transfers 9 7 9 1 6 Accessing the PSTAT Register 9 7 9 2 Programmer...

Page 263: ...9 1 shows the DSP PHIF unit at the block level The data path of the PHIF is comprised of a 16 bit input buffer pdx0 IN and a 16 bit output buffer pdx0 OUT Two DSP interrupts indicate the status of th...

Page 264: ...the output data strobe with respect to the DSP In Motorola mode PIDS is renamed PRWN parallel read write not and selects between a read and a write PODS is renamed PDS and becomes the data strobe for...

Page 265: ...low so the low byte from the pdx0 OUT register is placed on PB If PODS is driven high by the external device the data is latched externally and the DSP can again 3 state the PB The timing of this acti...

Page 266: ...is transferred to the low byte of the pdx0 IN register If PIDS is driven high by the external device the data is latched by the DSP The timing of this action is controlled by PIDS or PCSN whichever g...

Page 267: ...he two goes low last PBSEL byte select is low so the low byte from the pdx0 OUT register is placed on PB If PDS is driven high by the external device the data is latched externally and the DSP can aga...

Page 268: ...w last PBSEL byte select is low so the data is transferred to the low byte of the pdx0 IN register If PODS PDS is driven high by the external device the data is latched by the DSP The timing of this a...

Page 269: ...state of pdx0 IN pdx0 OUT and the flags are unaffected and no internal interrupt is generated Table 9 1 describes the PSTAT register The functional timing sequence for polling the PSTAT register is th...

Page 270: ...red resulting in the following default configuration PHIF always enabled PBSEL internally tied to zero Intel protocol 8 bit transfers pdx0 low byte selected or PSTAT selected if PSTAT pin is asserted...

Page 271: ...tes PSTRB This field defines PDS Motorola mode as active high or active low PBSELF PBSELF determines whether a one on the PBSEL byte select pin corresponds to a high byte or to a low byte PFLAG PFLAG...

Page 272: ...rrupt request the IACK interrupt acknowledge signal is asserted and the interrupt service routine is started When the interrupt routine is completed by reading or writing pdx0 IACK is negated becomes...

Page 273: ...n interrupt during the next instruction After this instruction has executed the interrupts are disabled Therefore to protect an instruction sequence from interrupts follow the command to mask the PIBF...

Page 274: ...x0 OUT is emptied It is assumed that POBE is enabled in the inc register and no other interrupts are pending These actions occur during the time intervals labelled on the timing diagram A The POBE int...

Page 275: ...Chapter 10 Bit I O Unit...

Page 276: ...dware Function 10 1 10 1 1 BIO Configured as Inputs 10 2 10 1 2 BIO Configured as Outputs 10 2 10 1 3 Pin Descriptions 10 3 10 1 4 BIO Pin Multiplexing 10 4 10 2 Software View 10 4 10 2 1 Registers 10...

Page 277: ...ribes the BIO hardware function and the software view including register encodings sample pro grams and pertinent instructions 10 1 BIO Hardware Function Figure 10 1 is the block diagram for the BIO E...

Page 278: ...y are somef some bits false somet some bits true allf all bits false and allt all bits true 5 4199 Figure 10 2 BIO Configured as Inputs 10 1 2 BIO Configured as Outputs If the DIR field of sbit has se...

Page 279: ...DSP has placed on the device pins If a BIO pin is switched from being an output to being an input and then back to being an output the pin remembers the previous output value 5 4203 Figure 10 3 BIO Co...

Page 280: ...ven high 10 2 Software View The cbit and sbit registers the flags and the pertinent instructions make up the software view Figure 10 4 is a flow diagram showing the decisions made for each bit to dete...

Page 281: ...xxxxxx IOBIT6 is an output input if 0 xx1xxxxx IOBIT5 is an output input if 0 xxx1xxxx IOBIT4 is an output input if 0 xxxx1xxx IOBIT3 is an output input if 0 xxxxx1xx IOBIT2 is an output input if 0 xx...

Page 282: ...an accumulator or with immediate data They can be read to memory or to an accumu lator The flags that are set by the BIO are included in the general set of flags that are tested by the conditional bra...

Page 283: ...are outputs bits 3 0 are inputs a0 sbit read current value in sbit register a0 a0h 0x000f mask off all but the 4 inputs a0 now holds the current value on BIO 3 0 cbit 0x0000 initialize BIO bits 7 4 to...

Page 284: ...Chapter 11 JTAG Test Access Port...

Page 285: ...n Register JIR 11 7 11 3 4 The Boundary Scan Register JBSR 11 8 11 3 5 The Bypass Register JBPR 11 16 11 3 6 The Device Identification Register JIDR 11 16 11 3 7 The JTAG Data Register jtag 11 19 11 3...

Page 286: ...es and on chip support of the hardware development system on chip emulation The full description of the custom features is beyond the scope of this manual An overview of the JTAG architecture follows...

Page 287: ...te machine that controls the operation of the test logic as defined by the standard The TMS input value sampled on the rising edge of TCK controls the state transi tions The state diagram underlying t...

Page 288: ...serially Section 11 3 6 The Device Identification Register JIDR expands on the JIDR structure and function jtag Register jtag jtag is a 16 bit scannable data register used for communicating data or c...

Page 289: ...n test clock in a board environment the slowest JTAG design determines the common clock frequency TMS is the test mode select input pin It controls test operations by determining the current state of...

Page 290: ...he TAP controller and the instruction decoder A brief description of the TAP controller states follows Test Logic Reset The test logic is disabled while the controller is in this state so normal opera...

Page 291: ...Figure 11 3 shows two independent actions occurring data parallel loaded into the test data register and shifted out on TDO and new data being shifted into the DSP test data register and then enabled...

Page 292: ...between the JIR and the selected TDR depending on whether the TAP Controller is in an IR scan cycle or a DR scan cycle All four cells of JIR have the capability of loading the shift register stage fro...

Page 293: ...the boundary scan register as specified by the standard All of the cells contain a parallel output stage that is updated on the falling edge of TCK New data will appear only in the update DR state un...

Page 294: ...ols cell 86 48 B OCK1 85 B IOBIT1 PB5 49 B OLD1 86 B IOBIT2 PB6 50 DC Controls cell 49 87 B IOBIT3 PB7 51 DC Controls cell 53 88 B VEC3 IOBIT4 52 O DO1 89 B VEC2 IOBIT5 53 B SYNC1 90 DC Controls cell...

Page 295: ...C Controls cell 87 50 O IBF1 87 B SADD2 PB3 51 I DI1 88 DC Controls cell 89 52 DC Controls cell 53 89 B IOBIT0 PB4 53 B ILD1 90 DC Controls cell 91 54 DC Controls cell 55 91 B IOBIT1 PB5 55 B ICK1 92...

Page 296: ...R register The MODE signal is equal to one during EXTEST and INTEST and is equal to zero during SAMPLE and in the test logic reset state i e during normal device functions The CAPTURE SHIFT and UPDATE...

Page 297: ...ry similar to the I type cells They consist of a shift register stage with parallel input load capability during the capture DR state and parallel load into the output stage during the update DR state...

Page 298: ...AFTCOPY 11 13 11 3 Elements of the JTAG Test Logic continued 11 3 4 The Boundary Scan Register JBSR continued 5 4207 Figure 11 6 Cell Interconnections for a 3 State Pin OUTPUT PIN DI PO SO PIN OUTPUT...

Page 299: ...e logic and the HOLI signal corresponds to the direction control signal from the device In this case the cell s output to the pin PO is tied to the corresponding signal from the device DO and the cell...

Page 300: ...r cell types in mind Figure 11 6 and Figure 11 8 show cell interconnec tions for a 3 state output pin and for a bidirectional pin Note In the DSP1611 17 18 27 28 29 all output pins are 3 statable 5 42...

Page 301: ...r scan cycle after powerup Those devices with an ID register will produce a 32 bit pattern starting with a one see the JIDR descrip tion below and those without an ID register will produce a single ze...

Page 302: ...he shift DR state The following table summarizes the fields of JIDR for the DSP1617 18 27 28 29 only Table 11 5 JIDR Field Descriptions DSP1617 18 27 28 29 Bit 31 30 29 28 27 19 18 12 11 0 Field RESER...

Page 303: ...1 only follows The Manufacturer Identity Field Bits 11 0 of the JIDR make up the manufacturer identity field containing a compressed form of the JEDEC standard manufacturer s identification code The a...

Page 304: ...description of the individ ual JTAG instructions covered briefly in Section 11 2 Overview of the JTAG Instructions is presented Because the description of a JTAG instruction is intimately tied to the...

Page 305: ...ated into the boundary scan register cells through the TAP Controller transitions capture DR exit1 DR and update DR while the SAMPLE instruction loads a safe pattern into the output stage of JBSR This...

Page 306: ...Chapter 12 Timer...

Page 307: ...1 Hardware View 12 1 12 2 Programmable Features and Operation 12 2 12 2 1 timerc Register Encoding 12 2 12 2 2 timer0 Register 12 3 12 2 3 The inc Register 12 3 12 2 4 Initialization Conditions 12 3...

Page 308: ...the repeated operation Bit 6 DISABLE powers down the timer for reduced power in sleep mode Bit 4 in the powerc register TIMERDIS performs the same function i e powering down the timer Bit 7 can be re...

Page 309: ...T0EN 0 Hold current count T0EN 1 Count toward zero Prescale Field Frequency of Interrupts CKO free running non wait stated clock Period at CKI 16 67 ns 60 MHz 2x Clock Period at CKI 25 ns 40 MHz 1x C...

Page 310: ...12 2 2 timer0 Register The second register in the interrupt timer block is named timer0 Upon writing to this register both the timer itself and the optional reloadable period register are written with...

Page 311: ...handler at INT5 vector start auc 0 perform initializations timer0 1250 interrupt every 1250 ticks of timer TCLK timerc 0x34 set input clock to CKO 32 1 25 MHz and enable RELOAD and timer0 counting in...

Page 312: ...is if this instruction appears on the instruction data bus XDB Five instruction cycles CKO later the first count occurs when the counter decrements to one At time slot 9 it decrements to zero and the...

Page 313: ...Chapter 13 Bit Manipulation Unit...

Page 314: ...13 1 Hardware View 13 1 13 2 Software View 13 2 13 2 1 Instruction Set 13 2 13 2 2 Shifting Operations 13 2 13 2 3 Normalization 13 4 13 2 4 Extraction 13 5 13 2 5 Insertion 13 6 13 2 6 Shuffle Accum...

Page 315: ...erations of the BMU They store a value that determines the amount of shift or the width and offset fields for bit extraction or insertion Alternately an immediate data word transferred over the IDB ca...

Page 316: ...ource accumulator and the destination accumulator can be the same or different If the source and destination accumulators are different the source remains the same after the shift The amount of shift...

Page 317: ...t bits 35 0 in the source accumulator are shifted to the right into the destination accumulator The open upper bits are filled in with the sign bit of the source accumulator 5 4134 Figure 13 4 Arithme...

Page 318: ...n bits so shift left three times in order that the last sign bit ends up in the MSB position For the DSP the number E of redundant sign bits is found with respect to sign bit 31 If an overflow has occ...

Page 319: ...of the LSB of the field which is the offset of the field Pictorially 5 4215 Figure 13 5 Extraction The instructions are as follows aD extracts aS IM16 Get field from immediate IM16 and sign extend Fo...

Page 320: ...ruction however it is implied in Case 2 see page 7 In both cases the field width and offset are defined by an immediate data word or data in one of the arM registers Case 1 The source aS and destinati...

Page 321: ...S 5 4135 Figure 13 7 Insertion Case 2 Source and Destination Accumulators Are the Same The instructions are as follows aD insert aS IM16 Get field from immediate IM16 and insert aD insert aS arM Get f...

Page 322: ...the two alternate accumulators The contents of accumulator aD are replaced with the contents of alternate accumulator aaT and the contents of aaT are replaced with the contents of accumulator aS aD an...

Page 323: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field T D S F4 3 1 0 F4 0 ar 3 0 Immediate Operand IM16 F4 ar Operation 0000 00xx aD aS arM 0001 00xx aD aS arM 0000 10xx aD aS arM 0001 10xx aD aS arM 1000 0000 aD...

Page 324: ...cumulator a0 in the form 0 0 0 0 0 0 0 0 S n2 n1 n0 m3 m2 m1 m0 A previous routine _mulin for the DSP16 16A is found in the application library The comparison between the two routines is Routine Sourc...

Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...

Page 326: ...equence 14 6 14 4 Operation of the ECCP 14 7 14 5 Software Architecture 14 8 14 5 1 R Field Registers 14 8 14 5 2 ECCP Internal Memory Mapped Registers 14 10 14 5 3 ECCP Interrupts and Flags 14 17 14...

Page 327: ...by the contents of the address register After each edr access the contents of the address register is postincremented by one Upon writing an ECCP opcode to instruction register eir either MLSE equali...

Page 328: ...de of the ECCP The symbol registers S0H0 S5H5 ZIG10 and ZQG32 the generating polynomial registers ZIG10 ZQG32 and G54 and the channel impulse registers S0H0 S5H5 are used as input to the ECCP for MLSE...

Page 329: ...tate transitions is calculated as where and The absolute values of the difference signal are saturated at the level 0xFF The sixteen most significant bits of this 17 bit incremental branch metric are...

Page 330: ...of the internal RAM RAM4 The accumulated cost of the path p at the Jth instant ACC J p is the sum of the incremental branch metrics belonging to the path p up to the time instant J The update unit co...

Page 331: ...uction and it generates the EOVF interrupt if an overflow in the accumulated cost is imminent The EBUSY flag indicates if the ECCP is in operation 14 2 5 Traceback RAM As noted previously the fourth 1...

Page 332: ...r convolve operation is performed and an invalid symbol is available The subsequent rows follow as shown 5 4501 Figure 14 2 DSP Core Operation Sequence EBUSY FALSE ECCP OFF LOAD ECCP EBUSY TRUE ECCP O...

Page 333: ...on and finally unloading the decoded symbol from the ECCP The operation of the ECCP is captured in the signal flow diagram in Figure 14 3 5 4502 Figure 14 3 ECCP Operation Sequence DSP PROGRAMS ECCP D...

Page 334: ...a from the internal register addressed by ear and increment ear by one count The DSP writes instructions directly to the eir register to start a particular operation of the ECCP 5 4503 Figure 14 4 Reg...

Page 335: ...onics The UpdateMLSE instruction and the UpdateConv instruction each perform an appropriate branch metric calcula tion a complete Viterbi add compare select operation and a concurrent traceback decodi...

Page 336: ...Bits 31 24 are zero Bits 23 16 are most significant byte of path cost 0x0280 0x03FF Reserved Bits 15 0 are addressed by odd address Bits 15 0 are lower 2 bytes of path cost 0x400 Current Symbol Pointe...

Page 337: ...al decoding case Bits 7 0 are reserved Bits 15 8 are S0 MLSE equalization case Bits 7 0 are HQ0 Bits 15 8 are HI0 0x409 Decoded Symbol Register DSR Bits 7 0 are zero Bits 15 8 are decoded symbol 0x40A...

Page 338: ...the control register set the constraint length for convolutional decoding or MLSE equalization For hard decision convolutional decoding constraint lengths from 2 to 7 are supported The hard decision...

Page 339: ...1 MAN of the ECON regis ter Soft Decode Soft decode SD bit 0 of the control register selects one of two possible soft symbol definitions The soft decision data can be set to the coded surviving branch...

Page 340: ...ank of the internal RAM RAM4 This pointer will be incremented after each UpdateMLSE and UpdateConv instruction It is a modulo 32 count for soft symbol decision and modulo 64 count pointer for hard sym...

Page 341: ...cated at 0x200 0x27F Two consecutive addresses are allocated to access each of these 24 bit registers The even addresses starting with address zero will access bits 23 to 16 of an update field padded...

Page 342: ...5 The symbol registers consist of six words at address locations 0x403 to 0x408 the contents of which are used for branch metric calculations For convolutional decoding the upper bytes of these six wo...

Page 343: ...sed Two vectored interrupts are EREADY and EOVF These interrupts are maskable through the inc register and their status can be read or changed by using the ins register utilizing the DSP1600 interrupt...

Page 344: ...length field of the ECON register Any user data or code in RAM4 must reside outside these address ranges 2 Access to RAM4 data and execution of code from RAM4 can be performed only during periods of E...

Page 345: ...f instruction cycles is measured from the time when the eir register is written with the ECCP command to the time when the output data is ready in the edr register 14 6 1 ResetECCP Instruction The Res...

Page 346: ...UpdateMLSE instruction CL has a maximum value of four corresponding to constraint length 6 For the UpdateMLSE instruction with soft decision the traceback length register can be programmed to a maxi...

Page 347: ...lue programmed into the TBLR register Table 14 7 shows some representative values for the UpdateMLSE instruction cycles for different values of CL and TBLR For the UpdateMLSE instruction CL has a maxi...

Page 348: ...ON register and TBLR is the traceback length value programmed into the TBLR register Table 14 8 shows some representative values for the UpdateConv instruction cycles with the soft decision mode selec...

Page 349: ...each a maximum value of 63 with the hard decision decoding mode selected 14 6 6 TraceBack Instruction The length of the TraceBack instruction is only a function of the programmed traceback length and...

Page 350: ...Chapter 15 Interface Guide...

Page 351: ...ntrol I O Interface 15 9 15 2 5 Control I O Interface 15 11 15 2 6 JTAG Test Interface 15 11 15 3 Resetting DSP161X and DSP162X Devices 15 12 15 3 1 Powerup Reset 15 12 15 3 2 Using the TAP to Reset t...

Page 352: ...est Clock Mask Programmable Input Clock Option TTL CMOS Small Signal Crystal Oscillator CMOS CKI I CKI CKI VIN XLO 10 pF capacitor to VSS CKI VDD CKI2 P or I VDD open VIN XHI 10 pF capacitor to VSS op...

Page 353: ...st Mode Select TDI I JTAG Test Data Input TDO O JTAG Test Data Output DOEN1 I O SIO1 Data Output Enable SADD1 I O SIO1 Multiprocessor Address STOP I STOP Input Clock This pin is VDD in the x11 SYNC1 I...

Page 354: ...F capacitor to VSS CKI CKI2 I VSSA VCM XHI 10 pF capacitor to VSS open VEC0 IOBIT7 I O Vectored Interrupt Indication 0 Status Control Bit 7 VEC0 IOBIT7 I O Vectored Interrupt Indication 1 Status Contr...

Page 355: ...ssor Address SYNC1 I O SIO1 Multiprocessor Synchronization DO1 O SIO1 Data Output OLD1 I O SIO1 Output Load OCK1 I O SIO1 Output Clock ICK1 I O SIO1 Input Clock ILD1 I O SIO1 Input Load DI1 I SIO1 Dat...

Page 356: ...on 15 4 Mask Pro grammable Options Tables 15 3 and 15 4 CKI2 Input Clock 2 Used with mask programmable input clock options that require an external crystal or small signal differential across CKI and...

Page 357: ...nstruction is executed TRAP Trap Signal Positive assertion If asserted the processor is put into the trap condition that normally causes a branch to the location 0x0046 The hardware development system...

Page 358: ...n If asserted the signal indicates an access to external data memory addresses 0x8000 through 0xFFFF see Table 3 7 This signal s leading edge can be delayed via the ioc register see Table 6 13 ERAMLO...

Page 359: ...s either LSB or MSB first according to the sioc register MSB field DO1 changes on the rising edges of OCK1 For the DSP1627 28 29 DO1 changes on the rising or falling edge of OCK1 corresponding to the...

Page 360: ...in multiplexes a parallel I O interface with a second serial I O interface and a 4 bit I O interface The interface selection is made by writing the ESIO2 bit in the ioc register see Section 6 2 Progra...

Page 361: ...e data can be placed on the PB bus by an external device In both active and passive modes the DSP1617 reads the contents of the PB bus on the rising edge low to high transition of PIDS PODS PDS Parall...

Page 362: ...ernal circuitry allows the device to be controlled through the JTAG port to provide on chip in circuit emulation Lucent Technologies provides hardware and soft ware tools to interface to the on chip H...

Page 363: ...DSP can be controlled by external pins This is achieved by forc ing the TAP Controller2 into the Test Logic Reset TLR state In the TLR and device reset states all bidirectional pins are 3 stated and a...

Page 364: ...serted will 3 state all output and bidirectional pins except TDO which is controlled by only by the TAP Controller If INT0 is not asserted while RSTB is asserted EROM ERAMHI ERAMLO IO and RWN outputs...

Page 365: ...ystem HDS provides on chip in circuit emulation and requires that the relocatable HDS monitor routine be linked to the application code This code s object file is called 1617hds v 1618hds v 1627hds v...

Page 366: ...rovide testing of the inter nal ROM contents a cyclic redundancy check CRC program is called by and linked to the user s source code The CRC code crc16 v must be entirely contained in the first 4 Kwor...

Page 367: ...Appendix A Instruction Encoding...

Page 368: ...APPENDIX A INSTRUCTION ENCODING CONTENTS A Instruction Encoding A 1 A 1 Instruction Encoding Formats A 1 A 2 Field Descriptions A 4...

Page 369: ...g Formats Multiply ALU Instructions Format 1 Multiply ALU Read Write Group Format 1a Multiply ALU Read Write Group Format 2 Multiply ALU Read Write Group Format 2a Multiply ALU Read Write Group Specia...

Page 370: ...s Format 4 Branch Direct Group Format 5 Branch Indirect Group Format 6 Conditional Branch Qualifier Software Interrupt icall Note A branch instruction immediately follows except for a software interru...

Page 371: ...Data Move Group Format 8 Data Move immediate operand 2 words Format 9 Short Immediate Group Format 9a Direct Addressing Cache Instructions Format 10 do redo Bit 15 11 10 9 4 3 0 Field T a R Y Z Bit 1...

Page 372: ...ble A 2 B Field B Operation 000 return 001 ireturn 010 goto pt 011 call pt 1xx Reserved T T T T Table A 3 BMU Encodings F4 AR Operation 0000 00nn aD aS arM 0001 00nn aD aS arM 0000 10nn aD aS arM 0001...

Page 373: ...00010 eq 10010 allt 00011 ne 10011 allf 00100 lvs 10100 somet 00101 lvc 10101 somef 00110 mvs 10110 oddp 00111 mvc 10111 evenp 01000 heads 11000 mns1 01001 tails 11001 nmns1 01010 c0ge 11010 npint 01...

Page 374: ...med Table A 7 F1 Field F1 Operation 0000 aD p p x y 0001 aD aS p p x y 0010 p x y 0011 aD aS p p x y 0100 aD p 0101 aD aS p 0110 nop 0111 aD aS p 1000 aD aS y 1001 aD aS y 1010 aS y 1011 aS y 1100 aD...

Page 375: ...short immediate data move instructions JA Field 12 bit jump address K Field Number of times the N instructions in cache are to be executed Zero specifies use of value in cloop register N Field Number...

Page 376: ...a 111001 Reserved 011010 sdx 111010 ar0 011011 tdms 111011 ar1 011100 pioc 111100 ar2 011101 pdx0 111101 ar3 011110 pdx1 111110 Reserved 011111 ybase 111111 alf Table A 12 R Field for DSP1611 18 27 28...

Page 377: ...nds 00 aSl IM16 10 aSh IM16 01 aS aT 11 aS p Table A 16 T Field T Operation Format 0000x goto JA 4 00010 short imm j k rb re 9 00011 short imm r0 r1 r2 r3 9 00100 Y a1 l F1 1 00101 Z aT l F1 2a 00110...

Page 378: ...indirect addressing with postmodification Z Field Z field specifies the form of register indirect compound addressing with postmodification Table A 17 X Field X Operation Two Operand Multiply ALU 0 p...

Page 379: ...Appendix B Instruction Set Summary...

Page 380: ...B 17 if CON F2 B 18 ifc CON F2 B 19 F1 Y B 20 F1 Y a0 l B 22 F1 Y a1 l B 22 F1 x Y B 24 F1 y l Y B 26 F1 y Y x pt i B 28 F1 y a0 x pt i B 30 F1 y a1 x pt i B 30 F1 aT l Y B 32 F1 Y y l B 34 F1 Z y l B...

Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...

Page 382: ...d page The lower 12 bits of the PC are written with the 12 bit immediate value of JA The upper 4 bits of the PC remain unchanged the goto pt instruction is used for branches outside the current 4 Kwor...

Page 383: ...e 16 bit value of the register The following branch destinations are specified in the B field B Field Action 000 return same as goto pr 001 ireturn same as goto pi 010 goto pt 011 call pt For this ins...

Page 384: ...ome BIO bits true 00101 lvc logical overflow clear 10101 somef some BIO bits false 00110 mvs math overflow set 10110 oddp BMU odd parity result 00111 mvc math overflow clear 10111 evenp BMU even parit...

Page 385: ...alue of JA The upper 4 bits of the PC remain unchanged the call pt instruction is used for subroutine calls outside the current 4 Kword page Note The call JA instruction should not be placed in the la...

Page 386: ...called just as it would be by an external interrupt The interrupt return register is set to PC 1 and the PC is set to two to start execution at the interrupt handler Note that icall vectors to memory...

Page 387: ...ll be decremented to zero at the end of the do instruction Notes on cache performance The do instruction executes in one cycle When the cache is used to repeat a block of N instructions the cycle timi...

Page 388: ...n from the value in the cloop register that must contain a value between 1 and 127 inclusive The cloop register will be decremented to zero at the end of the redo instruction Notes on cache performanc...

Page 389: ...Rsrvd pdx4 Rsrvd Rsrvd 000010 r2 011000 sioc Registers sioc 1 2 srta 1 2 and tdms 1 2 are not readable 101101 Rsrvd pdx5 Rsrvd Rsrvd 000011 r3 011001 srta 101110 Rsrvd pdx6 Rsrvd Rsrvd 000100 j 01101...

Page 390: ...998 B 9 DRAFT COPY Lucent Technologies Inc R IM16 16 bit long immediate load continued Bit 15 14 13 12 11 10 9 4 3 2 1 0 Field word 1 0 1 0 1 0 0 R 0 0 0 0 word 2 Immediate Value IM16 Words 2 Cycles 2...

Page 391: ...ost significant bit of SR is the least significant bit of the T field used in the instruction set encodings in Table A 16 page A 9 2 When a DSP1611 17 18 27 28 29 program is encoded and if the immedia...

Page 392: ...ess than 16 bits load from the low order bits of aS l The value of S can be zero to select accumulator a0 or one to select accumulator a1 Register R is one of the gen eral sets of registers shown for...

Page 393: ...one to select a0 aT is encoded as aT in the instruction encodings in Appendix A Register R is one of the general sets of registers shown in Table B 2 on page B 8 for the long imme diate load except th...

Page 394: ...r x are the destination registers R the assembler assembles this instruction as a single cycle multiply ALU instruction If a two cycle move encoding is necessary the optional mnemonic move may be used...

Page 395: ...form for this instruction with a postincrement of one This imple ments a write to a stack in memory Register R is one of the general set of registers listed in Table B 2 on page B 8 under the long imm...

Page 396: ...eral sets of registers listed under the long immediate load instruction Register sources c0 c1 and c2 are less than 16 bits and are sign extended Register source auc is less than 16 bits and is zero e...

Page 397: ...Note The upper 11 bits of ybase are concatenated with the OFFSET to form the direct address The lower five bits of ybase are ignored For direct addressing register DR can be any of the following Writ...

Page 398: ...n page B 8 The OFFSET is a 5 bit direct address OFFSET from the ybase register and is specified in the opcode The OFF SET can have any value from 0 to 31 Note The upper 11 bits of ybase are concatenat...

Page 399: ...lso be per formed unconditionally i e written by themselves and encoded as a condition of true The F2 functions that can be conditionally performed i e encoded in the F2 field are as follows Note The...

Page 400: ...are encoded in the CON field see Table B 1 on page B 3 The F2 functions can also be performed unconditionally i e written by themselves and encoded as a condition of true The possible F2 special func...

Page 401: ...3 Arithmetic and Precision for the options of shifting the output of the p register into aS in the above operations 2 Access the Y space location pointed to by rM where rM is specified by the two mos...

Page 402: ...chnologies Inc F1 Y multiply ALU operation with postmodification of pointer register continued Bit 15 14 13 12 11 10 9 8 5 4 3 0 Field 0 0 1 1 0 D S F1 0 Y Words 1 Cycles 1 Group Multiply ALU Addressi...

Page 403: ...in parallel 1 Write the old value of a0 a1 a0l or a1l to the Y space location pointed to by rM where rM is specified by the two most significant bits of the Y field 00 r0 01 r1 10 r2 11 r3 The X fiel...

Page 404: ...lving the y register y is sign extended to 36 bits before performing the operation including logical operations See Section 3 3 Arithmetic and Precision for the options available when shifting the out...

Page 405: ...are modified based on the value computed by the DAU Note For all diadic operations involving the y register y is sign extended to 36 bits before performing the operation including logical operations...

Page 406: ...is specified by the two least significant bits of the Y field 2 LSBs of Y Action Symbol 00 no action rM 01 postincrement rM 10 postdecrement rM 11 Code 11 in this case means add the current value of t...

Page 407: ...d on the value computed by the DAU Note For all diadic operations involving the y register y is sign extended to 36 bits before performing the operation including logical operations See Section 3 3 Ar...

Page 408: ...is specified by the two least significant bits of the Y field 2 LSBs of Y Action Symbol 00 no action rM 01 postincrement rM 10 postdecrement rM 11 Code 11 in this case means add the current value of...

Page 409: ...elect a0 or one to select a1 Flags are modified based on the value computed by the DAU Note For all diadic operations involving the y register y is sign extended to 36 bits before performing the opera...

Page 410: ...ither internal or exter nal X space may be accessed depending on the address and the state of the EXM pin 5 Postmodify the value of the pt register by either one or i selected by the X field X 0 pt X...

Page 411: ...ote For all diadic operations involving the y register y is sign extended to 36 bits before performing the operation including logical operations See Section 3 3 Arithmetic and Precision for the optio...

Page 412: ...isters continued F1 y a1 x pt i continued 4 Postmodify the value of the pt register by either one or i selected by the X field X 0 pt X 1 pt i Bit 15 14 13 12 11 10 9 8 5 4 3 2 1 0 Field a0 1 1 0 0 1...

Page 413: ...he DAU Note For all diadic operations involving the y register y is sign extended to 36 bits before performing the operation including logical operations See Section 3 3 Arithmetic and Precision for t...

Page 414: ...cation is specified by the two least significant bits of the Y field 2 LSBs of Y Action Symbol 00 no action rM 01 postincrement rM 10 postdecrement rM 11 Code 11 in this case means add the current val...

Page 415: ...value computed by the DAU Note For all diadic operations involving the y register y is sign extended to 36 bits before performing the operation including logical operations See Section 3 3 Arithmetic...

Page 416: ...n is specified by the two least significant bits of the Y field 2 LSBs of Y Action Symbol 00 no action rM 01 postincrement rM 10 postdecrement rM 11 Code 11 in this case means add the current value of...

Page 417: ...ons involving the y register y is sign extended to 36 bits before performing the operation including logical operations See Section 3 3 Arithmetic and Precision for the options available when shifting...

Page 418: ...Z field The available options for the postmodification are specified as follows Symbol 2 LSBs of Z First Action Second Action rMzp 00 no action zero postincrement plus rMpz 01 postincrement plus no ac...

Page 419: ...including logical operations See Section 3 3 Arithmetic and Precision for the options available when shifting the output of the p register into aS in the above operations 2 Save either the y or yl reg...

Page 420: ...of the Z field The available options for the postmodification are specified as follows Symbol 2 LSBs of Z First Action Second Action rMzp 00 no action zero postincrement plus rMpz 01 postincrement pl...

Page 421: ...1 are as follows The value of S can be zero to select a0 or one to select a1 The value of D can be zero to select a0 or one to select a1 Flags are modified based on the value computed by the DAU Note...

Page 422: ...least significant bits of the Z field The available options for the postmodification are specified as follows 7 Access the X space location pointed to by pt and write this value into the x register Ei...

Page 423: ...OR operation writing a 36 bit result aD aS aT is 36 bit logical XOR operation writing a 36 bit result aS aT sets the flags on a 36 bit subtract No result is written aS aT sets the flags on a 36 bit l...

Page 424: ...is a 36 bit logical XOR operation writing a 36 bit result aS p sets the flags on a 36 bit subtract No result is written aS p sets the flags on a 36 bit logical AND No result is written The F3 field sp...

Page 425: ...ORed or XORed with aS writing a 36 bit result aSh IM16 The 16 bit value IM16 is aligned with bits 31 16 of aS IM16 is sign extended into the guard bits and bits 15 0 are padded with zeros The resulti...

Page 426: ...ed The following table provides the encoding for the F3 field F3 Field Operation 1000 aD aS h l IM16 1001 aD aS h l IM16 1010 aS h l IM16 1011 aS h l IM16 1101 aD aS h l IM16 1110 aD aS h l IM16 1111...

Page 427: ...the same type and vice versa aD a aS performs an arithmetic right shift aD a aS performs an arithmetic left shift aD a aS performs a logical right shift This instruction clears the guard bits bits 35...

Page 428: ...performs an arithmetic right shift aD aS arM performs an arithmetic left shift aD aS arM performs a logical right shift This instruction clears the guard bits bits 35 32 before shifting aD aS arM perf...

Page 429: ...IM16 performs an arithmetic right shift aD aS IM16 performs an arithmetic left shift aD aS IM16 performs a logical right shift This instruction clears the guard bits bits 35 32 before shifting aD aS...

Page 430: ...tive and an arithmetic right shift will be done to normalize the number see page B 50 E K 5 where K is the total number of bits that are the same starting from bit 35 and counting to the right For exa...

Page 431: ...35 and counting to the right For example 2 The 36 bit value in aS is then arithmetically shifted left by E the amount of this computed exponent and the 36 bit shifted value is placed in aD If aS has o...

Page 432: ...eight bits of arM hold the OFFSET from bit zero of aS in bits For example arM 0xe06 defines a 14 bit wide field starting from bit six of aS This copies bits 19 6 of aS to low order aD bits 13 0 and e...

Page 433: ...f the field in bits and the lower eight bits of IM16 hold the OFFSET from bit zero of aS in bits For example IM16 0xe06 defines a 14 bit wide field starting from bit six of aS This copies bits 19 6 of...

Page 434: ...ight bits of arM hold the WIDTH of the field in bits and the lower eight bits of arM hold the OFFSET from bit zero of a in bits For example arM 0xe06 defines a 14 bit wide field starting from bit six...

Page 435: ...ue IM16 The upper eight bits of IM16 hold the WIDTH of the field in bits and the lower eight bits of IM16 hold the OFFSET from bit zero of a in bits For example IM16 0xe06 defines a 14 bit wide field...

Page 436: ...ed with the old value in aaT A temp register is used for the exchange to provide a true swap All transfers are full 36 bit Flags are set based on the value written into aD Bit 15 14 13 12 11 10 9 8 7...

Page 437: ...Index...

Page 438: ...op 2 18 call JA 4 13 clock CKI 15 5 CKO 6 14 12 1 computation exponent 4 32 13 4 normalization 4 32 13 4 conditional instructions see instructions conditional control block 5 19 counter conditional mn...

Page 439: ...4 32 13 6 13 7 shuffle 13 8 cache 4 11 4 14 4 15 5 18 conditional and counters 5 4 5 6 control 4 11 4 12 4 13 data move 4 11 4 15 4 18 multiply ALU 4 11 special function 4 11 4 19 4 21 interrupt EMUXB...

Page 440: ...alization computation see computation normal ization O offset 14 18 operation interrupt 3 32 3 38 single cycle squaring 3 21 4 24 operations concurrent 2 2 overflow 5 3 P phase lock loop see PLL pin m...

Page 441: ...MODE field 9 7 9 9 PSOBEF field 9 10 PSTRB field 9 9 PSTROBE field 9 9 pi 2 18 5 7 5 11 5 12 pioc 8 1 8 2 8 15 8 16 IBF field 8 20 INT0 field 8 20 OBE field 8 20 PIDS field 8 20 PODS field 8 20 pllc 3...

Page 442: ...5 S saturation see register auc SAT field shift arithmetic left 13 3 arithmetic right 13 3 logical left 13 3 logical right 13 2 signal AB 6 2 15 6 CKI2 15 5 CKO 6 2 15 5 DB 6 2 15 6 DI 7 12 DI1 15 8 D...

Page 443: ...s port see JTAG TAP timer 2 22 12 1 prescaler 12 1 timer0 12 1 12 2 12 5 timerc 12 1 TIMERDIS 12 1 12 3 trap 3 29 3 38 3 39 V vectors interrupt X memory space 3 20 W wait state 3 8 6 1 6 13 6 17 X X a...

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