Lucent Technologies DSP1611, Information Manual

Page: 259 / 443

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Parallel I/O (DSP1617 Only)
Lucent Technologies Inc.
DRAFT COPY
8-21
8.4 PIO Signals
Table 8-7. PIO Signals
Symbol Type
†
† I = input; O = output.
Name/Description
PB[7:0] I/O
‡
‡ 3-stated.
PIO Data Bus. This 8-bit bidirectional bus is used to input data to or output data
from the PIO. It is 3-stated by the DSP unless PODS is low.
PSEL[2:0] I/O
‡
Peripheral Select 0—2. When both input and output are in active mode, this 3-bit
field is an output that can be decoded to determine which of the eight logical chan-
nels (pdx<0—7>) data is to be conveyed to or from. If the PIO is set up to have
passive input or output, PSEL2 becomes an input that acts as a chip select. In this
capacity, the chip is selected if PSEL2 is low.
PSEL1 I/O
‡
When active output mode is used, PSEL1 and PSEL0 form a 2-bit field selecting
between four channels (pdx<0—3>). When passive output mode is used, PSEL1
becomes an input. If driven high, the PIO will output the contents of the PSTAT reg-
ister; otherwise, it will output the contents of pdx. PSEL0 is always an output.
PSEL0 O
‡
As long as either input or output is configured for active mode, this pin indicates
which channel is being written. When both input and output are in passive mode,
PSEL0 becomes the logical OR of PIBF and POBE.
PIDS I/O
‡
Parallel Input Data Strobe. Negative assertion. In active mode, PIDS is an
output. When PIDS is driven low, data can be placed onto the PB bus. When PIDS
goes high, data should be removed from the PB bus. PIDS is asserted by the DSP
during active mode read transaction. In passive mode, PIDS is an input. When
asserted by an external device, this signal indicates that data is available on the PB
bus. In both passive and active modes, the trailing edge (low-to-high transition) of
PIDS is the sampling point.
PODS I/O
‡
Parallel Output Data Strobe. Negative assertion. In active mode, PODS is an
output. When PODS goes low, data is available on the PB bus. PODS is asserted
by the DSP during an active mode write transaction. In passive mode, PODS is an
input. When PODS is driven low by an external device, the DSP places the con-
tents of its parallel output register (pdx<0—7>) onto the PB bus.
PIBF O
‡
Parallel Input Buffer Full. Positive assertion. When PIDS is placed in active
mode, this flag is cleared. It is also cleared after reset. It can only be set when
PIDS is passive. It is set one cycle after the rising edge of PIDS indicating that data
has been latched into the pdx [IN]. When the DSP reads the contents of this regis-
ter emptying the buffer, the flag is cleared.
POBE O
‡
Parallel Output Buffer Empty. Positive assertion. When PODS is placed in active
mode, this flag is cleared. It is also cleared after reset. It can only be set when
PODS is passive. In this case, it is set one cycle after the rising edge of PODS indi-
cating that the data in pdx[OUT] has been driven onto the PB bus. When the DSP
writes to this register filling the buffer, the flag is cleared.