Lucent Technologies DSP1611, Information Manual, Page: 428 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Instruction Set Summary April 1998
B-47
DRAFT COPY
Lucent Technologies Inc.
aD = aS SHIFT arM
(shift value in aS by arM bits)
(aD)
←
(aS) >> (arM)
(aD)
←
(aS) << (arM)
(aD)
←
(aS) >>> (arM)
(aD)
←
(aS) <<< (arM)
These shift operations use the barrel switch in the BMU to perform shifts by a number in arM. The 36-bit value in
aS is shifted by the number of bits specified by the value in arM, and the 36-bit result is written to aD. If the shift
value is negative, the direction of the shift will automatically be reversed; i.e., a right shift will become a left shift of
the same type and vice versa.
aD = aS >> arM performs an arithmetic right shift.
aD = aS << arM performs an arithmetic left shift.
aD = aS >>> arM performs a logical right shift. (This instruction clears the guard bits [bits 35—32] before
shifting.)
aD = aS <<< arM performs a logical left shift.
Flags are set based on the value written into aD. For left shifts, the LLV flag is set if any significant bits are lost from
the value written into aD. For right shifts, the LLV flag is set if the shift amount is greater than 35 bits. The SHIFT
field selects the type of shift to perform:
00 - >> 01 - >>> 10 - << 11 - <<<
The M field selects one of the four ar registers:
00 - ar0 01 - ar1 10 - ar2 11 - ar3
Bit 15 14 13 12 11 10 9 8 7 6 5 4—3 2 1—0
Field
1 1 1 1 0 D S 0 0 0 0 SHIFT 0 M
Words: 1
Cycles: 1
Group: BMU
Addressing: Register
Flags affected: LMI, LEQ, LLV, LMV,
ODDP, EVENP, MNS1, NMNS1
Interruptible: Yes
Cacheable: Yes
Format: 3b