DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Information Manual
Bit I/O Unit
April 1998
10-2
DRAFT COPY
Lucent Technologies Inc.
(continued)
10.1.1 BIO Configured as Inputs
is a block diagram for the BIO, and all pins are programmed by the sbit register to be inputs.
Bits [15:8] of the sbit register (DIRection) select input or output for each IOBIT pin. Bits [7:0] of sbit hold the
VALUE from the device pins and hold this VALUE whether the pin is an input or an output. The VALUE field can be
read over IDB but not written. The cbit register in the input mode contains a MASK field and a PATTERN field that
define a comparison with the input data from the pins. The MASK chooses bits to be ignored, and the PATTERN
encoding is actually compared with the unmasked bits in VALUE if a write to cbit occurs. Four flags are set based
on the comparisons. They are somef (some bits false), somet (some bits true), allf (all bits false), and allt (all bits
true).
5-4199
Figure 10-2. BIO Configured as Inputs
10.1.2 BIO Configured as Outputs
If the DIR field of sbit has selected a pin or pins as outputs, the meaning of the fields in sbit stay the same; that is,
they still contain the DIRection and the VALUE found on the device pins. The meaning of the bits in the cbit regis-
ter, however, changes on a bit-by-bit basis. Each bit in the upper byte of cbit affects the meaning of the corre-
sponding bit in the lower byte. The upper byte of cbit contains a MODE field in bits [15:8] and a DATA field in
bits [7:0]. If a bit in the MODE field is a one, it selects the toggle mode for which a one in the DATA field means
toggle the output and a zero in the DATA field means leave the output unchanged. If a bit in the MODE field is a
zero, it selects the data mode for which a one in the DATA field becomes an output one and a zero becomes an
output zero.
IDB
sbit
INPUT
BUFFERS
IOBIT[7:0]
cbit
COMPARE
LOGIC
16
8
8
FLAGS
PATTERN
MASK
15
8
7
0
VALUE
DIR
15
8
7
0
8
8
8
8
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...