Information Manual
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Lucent Technologies Inc.
DRAFT COPY
10-1
10 Bit I/O Unit
The Bit I/O (BIO) Unit for the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 provides eight
bidirectional pins for monitor or control functions. The pins are multiplexed with the PIO
1
/PHIF
2
and interrupt state
pins. The BIO features include:
Each pin can be an input or an output independent of the others and can be changed back and forth by the pro-
gram.
Data on inputs can be read directly into the DSP or can be compared with a stored pattern with or without
masking. Flags are set based on the result.
Data from the DSP can be placed directly on outputs, or the outputs can be toggled or left unchanged.
The BIO is mainly intended for status and control but is also useful for general data purposes.
This chapter describes the BIO hardware function and the software view including register encodings, sample pro-
grams, and pertinent instructions.
10.1 BIO Hardware Function
is the block diagram for the BIO. Eight bidirectional pins (IOBIT[7:0]) go off-chip from the BIO. The
interface to the internal part of the DSP is through the internal data bus (IDB) and the flags. Data move instructions
transfer information to and from the BIO control registers over the IDB. The flags are set based on tests done on
the data on the IOBIT input pins.
5-4198
Figure 10-1. BIO Block Diagram
Two registers (cbit and sbit) are the main components in the BIO. They are used for control of the unit and transfer
of data. The upper byte of the sbit register controls the direction of each pin independently of the others.
10.1.1, BIO Configured as Inputs
Section 10.1.2, BIO Configured as Outputs
describe the BIO.
1.DSP1617 only.
2.DSP1611/18/27/28/29 only.
B I O
4
16
VE C[ 3:0] /I O BIT [7: 4]
MU X
MU X
FLAGS
DSP1611/17/18/27/28/29
PB[7:4]
IOBIT[7:0]
PB[7:4]/IOBIT[3:0]
VEC[3:0]
ioc (10)
ioc (12)
IDB
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...