Information Manual
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Serial I/O
Lucent Technologies Inc.
DRAFT COPY
7-7
7.1 SIO Operation
(continued)
7.1.3 Output Section (continued)
A serial address (SADD) transmits simultaneously with DO. The low-order 8 bits of this address are the transmit
address field of the srta register (bits 7—0) (see
). The high-order 8 bits of this address are obtained from
the low byte of the saddx register (bits 7—0). The SADD output is primarily intended for use in multiprocessor
mode and
Section 7.6, Multiprocessor Mode Description
should be consulted for its use in this application. The
SADD output can also be used as a second serial output only port if not in multiprocessor mode because the
SADD signal remains valid. (Do not confuse this with SIO2; SADD is a different port from the SIOs.)
If SADD is to be used as a second data port, the LD bit of the sioc register (bit 9) must be set high to synchronize
SADD with DO and the MODE bit of the tdms register (bit 8) must be set low to turn off multiprocessor mode.
Under these conditions, arbitrary values can safely be written to the srta register (low byte) and saddx register (low
byte) for 16-bit output transmissions. The high bytes of srta and saddx will be ignored in this application.
Note: The SADD output is active-low (inverted data). SADD must be pulled high through a resistor for multiproces-
sor applications.
The DOEN signal asynchronously enables the DO and SADD 3-state output buffers if active. Its operation is inde-
pendent of any other SIO signals.
shows the timing relationships for the SIO output port signals in active mode (active mode is defined
here as OLD being supplied by the DSP). The primary difference from passive mode is that OCK now drives OLD
and OLD is known to be a square wave.
5-4177
Figure 7-7. SIO Active Mode Output Timing, 16-bit Words
OLD
DO
SADD
OSE
OBE
DOEN
B0
B2 B3
B15
B0
B1
B1
AD0
AD7 AS0
AS7 AD0
AD7
OCK
DRIVE
3-STATE
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...