Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) April 1998
9-12
DRAFT COPY
Lucent Technologies Inc.
9.5 Overall Functional Timing
Figure 9-6 shows the overall timing diagram for an 8-bit read by an external device. Initially, the external device
drives PODS low enabling the data from the DSP onto PB and into the external device (assuming that PCSN is
low). When PODS goes high, the data is latched into the external device and the POBE interrupt goes high as the
pdx0(OUT) is emptied. It is assumed that POBE is enabled in the inc register, and no other interrupts are
pending. These actions occur during the time intervals labelled on the timing diagram:
A: The POBE interrupt is synchronized and latched in an interrupt pending latch.
B: The DSP is executing an interruptible instruction.
C, D: The DSP branches to the interrupt service routine (ISR) for POBE.
E. The DSP executes the first instruction in the ISR, for example,
pdx0 = a0
.
F: POBE is reset as the output buffer is written by the DSP. The external device can again strobe PODS.
G: The read cycle can then repeat. At least seven instruction cycles are required for the total read cycle.
5-4499
Figure 9-6. Overall PHIF Read Cycle
CKO
POBE
PODS
A B C D E F G