Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
External Memory Interface April 1998
6-26
DRAFT COPY
Lucent Technologies Inc.
6.6 Memory Sequencer
The DSP1611/17/18/27/28/29 pin-multiplexes the external ROM and RAM buses. Because some instructions
simultaneously access external ROM and RAM, a memory sequencer has been provided to eliminate any colli-
sions that might otherwise occur. Upon receiving the instruction, the sequencer will perform the X access first and
then the Y access transparently to the programmer. For example, let two instructions be executed: the first reads a
coefficient from EROM and writes data to ERAM; the second reads a coefficient from EROM and reads data from
ERAM. The sequencer carries out the following steps at the external memory interface: read EROM, write ERAM,
read EROM, and read ERAM. Each step is done in sequential one-instruction cycle steps assuming zero wait-
states are programmed. Note that the number of instruction cycles taken by the two instructions is four. In this
case, the write hold time is zero. If there are programmed wait-states for either the X access external memory seg-
ment or the Y access external memory segment, they must be added to the instruction time. The following formula
can be used to calculate the instruction cycles.
Instruction cycles = number of cycles (normal operation) + X
WS
+ Y
WS
+ 1
where: X
WS
= X programmed wait-states (mwait register)
Y
WS
= Y programmed wait-states (mwait register)
The sample code segment illustrates the problem.
rsect ".erom"
auc=0
a0=0
r0=data // r0 points to external RAM
loop: *r0++=a0 // external RAM access
a0h=a0h+1
a0h–0xa
if ne goto loop
end: goto end
.rsect".eram"
data: 10*int
The instruction at the label "loop" performs an access (write) to external RAM while the instruction itself is fetched
from external ROM.
If the extra cycles associated with the memory sequencer are not tolerated, there are two recommendations:
1. Place all read/write data (or all program and fixed data) in internal DPRAM, or
2. Use cache loops to perform the dual access.
The first simply suggests avoiding a dual access to external memory altogether. The second requires some expla-
nation. If instructions are executed in a cache loop as in the example that follows, the first pass through the loop
loads the cache memory and the instructions are executed as if they were out-of-cache. Every iteration thereafter
executes from within the cache. The first pass through the loop, however, uses the memory sequencer to fetch the
instruction and then performs the ERAM access. Actually, after the instructions are loaded into cache, dual access
disappears and the instruction fetch along with the additional cycles associated with the memory sequencer are
avoided during the second through N iterations.
Note: The reader is reminded that cache loops are noninterruptible.