Lucent Technologies DSP1611, Information Manual, Page: 77 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture April 1998
3-24
DRAFT COPY
Lucent Technologies Inc.
3.3 Arithmetic and Precision
(continued)
Shift Right 2 Bits (Figure 3-5)
If the auc[1:0] bits are 01, the data in the p register is shifted 2 bits to the right with respect to the bits in the accu-
mulator as product bits 31—2 are transferred into bits 29—0 of the accumulator. Bits p[1:0] are lost. The sign of
p (bit 31) is extended by 6 bits into bits 35—30 of the accumulator. This setting is most useful if avoiding overflow
is a primary consideration and the loss of the two LSBs of the product can be tolerated.
5-4113
Figure 3-5. p Register to Accumulator Bit Alignment, auc[1:0] = 01
x(16)
15 0
31 16 15
y(32)
p(32)
a0, a1(36)
0
31
0 35
2
30
29
1