Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Parallel I/O (DSP1617 Only) April 1998
8-2
DRAFT COPY
Lucent Technologies Inc.
8.1 PIO Operation
The PIO bus is an asynchronous interface. The PIO port characteristics are programmable and are controlled by
the pioc. The PIO can be accessed in two basic modes: active or passive. In active mode, the DSP drives the
data strobes (PIDS and PODS); and in passive mode, the external device drives these strobes. Input or output can
be configured in either of these modes independently.
In active mode, PIDS (parallel input data strobe) is an output that indicates if the PB bus is available during a read.
Likewise, PODS (parallel output data strobe) is an output that indicates if data is available on the bus during a write.
In passive mode, PIDS and PODS are inputs driven by an external device to latch data into and out of the PIO.
If PODS and PIDS are configured in opposite modes (i.e., the DSP controlling one and the user controlling the
other), the user must ensure that PODS and PIDS do not occur simultaneously.
8.1.1 Active Mode
The PIO is configured for active mode by proper initialization of bits 12 and 11 of the pioc (see Section 8.2.1, pioc
Register Settings ). If both input and output are configured for active mode, the three pins PSEL[2:0] are outputs of
the DSP that indicate which of the eight channels are being accessed. If either input or output is passive, some of
these pins become inputs and serve different purposes (see
Section 8.1.3, Passive Mode ).
The duration of active PIO strobe signals (PIDS and PODS) can be programmed by using bits 14 and 13 of the
pioc register.
Table 8-1 shows the possible configurations.
PIO transactions are executed with data move instructions to pdx[IN] or pdx[OUT]. Data move instructions are two
cycles long, and the minimum strobe width is one cycle. Therefore, with consecutive PIO instructions, the strobes
will have a 50% duty cycle.
Note: If the strobe widths are not minimum (pioc[14:13]
≠
00), consecutive PIO instructions are prohibited. Other
non-PIO instructions must be placed between two PIO instructions.
If pioc[14:13] = 01, an instruction or group of instructions taking one or more cycles must be placed between PIO
instructions.
If pioc[14:13] = 10, an instruction or group of instructions taking two or more cycles must be placed between PIO
instructions.
If pioc[14:13] = 11, a group of instructions taking three or more cycles must be placed between PIO instructions.
Any interrupt service routine must guarantee these conditions are met. As a simple rule if pioc[14:13] = 11, the
first instruction in an interrupt service routine cannot be a PIO instruction.
Table 8-1. PIO Strobe Widths
pioc Bits Strobe Width
14 13 PIDS
†
† T = 1 CKO clock period.
PODS
†
0 0 T T
0 1 2T 2T
1 0 3T 3T
1 1 4T 4T