Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Software Architecture
Lucent Technologies Inc.
DRAFT COPY
3-43
3.4 Interrupts
(continued)
3.4.7 Interrupts in DSP16A-Compatible Mode (DSP1617 Only) (continued)
sioint: /* service internal (IBF) interrupt */
a1=sdx /* reading sdx clears IBF */
pdx0=a1 /* DUMMY CODE */
ireturn
start:
pioc=0x1a20 /* enable IBF and INT0 interrupts */
/* active pio */
sioc=0x0 /* passive sio port */
srta=0x0
auc=0x0
40*nop
stop: goto stop
If the external interrupt is recognized while servicing an internal interrupt (less than one cycle between IACK and
INT0 being latched), the INT0 interrupt is pending and is serviced at the next interruptible instruction after the cur-
rent interrupt service routine has finished. In this case, unlike the DSP16A, there is no need to hold the INT0 signal
until the next rising edge of IACK. If the IBF interrupt is recognized while servicing the external interrupt, it is ser-
viced at the next interruptible instruction as in the previous case.
Therefore, given the interrupt service routine in the EXAMPLE , asserting INT0 with a pulse width of two clock peri-
ods guarantees the service of the concurrent internal and external interrupts under all conditions.
For concurrent external interrupts and if the external interrupt is being serviced as indicated by IACK and VEC1
high and if another external interrupt is requested again, the INT0 signal must be asserted until the next rising edge
of IACK (or VEC1).
For applications that need both concurrent internal and external interrupts, the INT0 pin can be asserted by a pulse
of two CKO periods if no other INT0 is pending or in progress; otherwise, INT0 must remain asserted in order to be
serviced again.