Lucent Technologies DSP1611, Information Manual, Page: 97 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture April 1998
3-44
DRAFT COPY
Lucent Technologies Inc.
3.4 Interrupts
(continued)
3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only)
Concurrent Internal and External Interrupts— Figure 3-16 shows the timing sequence of concurrent IBF and
INT0 interrupts with both interrupt signals synchronized to the falling edge of the CKO clock. Four cases are given
for different INT0 signals asserted at the same time as, or after, the IBF signal.
Case 1—INT0 is asserted the same time as IBF. They are latched internally at point A, and an interrupt is
caused by INT0 with both status bits in pioc set. INT0 in the pioc register is cleared when IACK goes low. IBF is
cleared upon reading of sdx.
Case 2—INT0 is asserted one clock cycle after IBF and latched internally at point B. Interrupt is caused by IBF
with both status bits in pioc set. ireturn does not clear INT0. In DSP16A, ireturn does clear INT0 in this case.
Case 3—INT0 is asserted two clock cycles after IBF and latched internally at point C. Interrupt is caused by IBF
with only IBF status bit set in the pioc register. INT0 is pending and is taken at the next interruptible instruction
after ireturn.
Case 4—INT0 asserted three clock cycles after IBF. This case is identical to case 3.
5-4121
† CKO is a zero-wait-stated clock.
Figure 3-16. Timing Sequence of Concurrent Internal and External Interrupts, DSP16A-Compatible Mode
CKO
†
IACK
A B C D
INT0 CASE 1
INT0 CASE 2
INT0 CASE 3
INT0 CASE 4
IBF