Information Manual
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Instruction Set
Lucent Technologies Inc.
DRAFT COPY
4-3
DSP1627/28/29, an instruction cycle is based on the frequency of the clock source that is selected (ring oscillator,
CKI, or clock synthesizer). Instructions are all one or two 16-bit words and, typically, execute in one or two instruc-
tion cycles.
4.3 Addressing Modes
There are three different locations for data in the DSP: in a register, in memory, or in an instruction. In this section,
addressing refers to the way the location of the data is specified in an instruction. The DSP1611/17/18/27/28/29
instructions use the following modes of addressing:
1. Register-direct: Data is already in a register and can be used directly in a command (e.g., p = x * y). The reg-
ister is specified in the instruction.
2. Register-indirect: Data is located in memory and is pointed to by an addressing register defined in the instruc-
tion.
3. Immediate: Data is located in part of a single-word instruction (short-immediate) or is the second word of a two-
word instruction (long-immediate). For a short immediate instruction, 9 bits of data can only be transferred to
one of the registers in the YAAU (except for ybase) and no other action occurs. For a long immediate instruc-
tion, two locations of program space are required so that 16 bits of data from the second word of the instruction
can be transferred to one of the general set of registers.
4. Compound addressing: A combination of the above cases 1 and 2 in which the data is in both a register and in
memory. A single instruction can call for a swap of the data. This is compound addressing; one addressing reg-
ister points to a memory location (or locations) for a read followed by a write. The instruction also specifies a
register for the swap, and the addressing register can be postmodified.
5. Direct-data addressing: A combination of case 1, 2, and 3 in which 5 bits from the instruction are concatenated
with 11 bits previously stored in the ybase register to form an address to Y-memory space. The instruction also
selects one of 16 registers to be the source or destination of data exchange with the Y memory.
6. Virtual-shift (modulo) addressing: A special case of register-indirect addressing in which an implicit circular
shift register is established for zero-overhead virtual-shift addressing. This mode enables the creation of an arbi-
trarily sized portion of contiguous RAM locations to behave as if it were a physical delay or shift register without
actually moving data within RAM. The virtual-shift buffer is implemented in memory by storing the data at fixed
locations and incrementing the memory pointer in a modular fashion. Virtual-shift addressing is described in
detail in
Section 5.3.4, Addressing Modes
.
4.3.1 Register Indirect Addressing
Indirect addressing allows a register to be used as a pointer to a memory location. The following instructions are
examples of register indirect addressing.
x=*pt++
*r0=y
The first instruction says to perform a memory read from the memory location pointed to by the pt register, put that
data in the x register, and increment the address in pt by one. The second instruction says to look at the address
in the r0 register and write the data from the y register (upper half) to the memory location in r0. In both cases, the
register r0 or pt is said to point to the data in memory because the register contains a 16-bit address for a memory
read or write.
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...