Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 JTAG Test Access Port
Lucent Technologies Inc.
DRAFT COPY
11-9
11.3 Elements of the JTAG Test Logic
(continued)
11.3.4 The Boundary-Scan Register—JBSR (continued)
Table 11-3. JTAG Scan Register (DSP1611, 1617 and 1618 Only)
Note: The direction of shifting is from TDI to cell 105, to cell 104, . . . , to cell 0, and to TDO.
Cell Type Signal Name/Function Cell Type Signal Name/Function
0—15 O AB[15:0] (cell #0 is AB0, etc.) 69 B OLD2/PODS
‡
16 I EXM 70 O IBF2/PIBF
‡
17 O RWN 71 DC Controls cell 75
18—21 O EROM, ERAMLO, ERAMHI, IO 72 DC Controls cell 74
22 O DSEL 73 O OBE2/POBE
‡
23—29 B DB[6:0] 74 B ICK2/PB0
‡
30 DC Controls cells 23—29, 31—39 75 B DI2/PB1
‡
31—39 B DB[15:7] 76 B DOEN2/PB2
‡
40 O OBE1 77 B SADD2/PB3
‡
41 O IBF1 78 DC Controls cell 77
42 I DI1 79 DC Controls cell 76
43 DC Controls cell 46 80 DC Controls cell 82
44 DC Controls cell 47 81 DC Controls cell 85
45 DC Controls cell 48 82 B IOBIT0/PB4
‡
46 B ILD1 83 DC Controls cell 87
47 B ICK1 84 DC Controls cell 86
48 B OCK1 85 B IOBIT1/PB5
‡
49 B OLD1 86 B IOBIT2/PB6
‡
50 DC Controls cell 49 87 B IOBIT3/PB7
‡
51 DC Controls cell 53 88 B VEC3/IOBIT4
‡
52 O DO1 89 B VEC2/IOBIT5
‡
53 B SYNC1 90 DC Controls cell 88
54 OE Controls cell 52 91 DC Controls cell 89
55 DC Controls cell 58 92 B VEC1/IOBIT6
‡
56 DC Controls cell 59 93 B VEC0/IOBIT7
‡
57 I STOP
†
94 I INT1
58 B SADD1 95 DC Controls cell 92
59 B DOEN1 96 DC Controls cell 93
60 DC Controls cell 63 97 I INT0
61 DC Controls cell 62 98 DC Controls cell 101
62 B OCK2/PSEL2/PCSN
‡
99 OE Controls cells 0—15,40—41,70,73,100
63 B DO2/PSEL1/PSTAT
‡
100 O IACK
64 B SYNC2/PSEL0/PBSEL
‡
101 B TRAP
65 DC Controls cell 64 102 O CKO
66 DC Controls cell 69 103 OE Controls cells 17—22,102
67 DC Controls cell 68 104 I RSTB
68 B ILD2/PIDS
‡
105 I
Clock Generator
§
† Shifting a zero into this cell in the mode to scan a zero into the device will disable the processor clocks the same as the STOP pin will.
‡ For descriptions of the pin multiplexing, see
Section 10.1.4, BIO Pin Multiplexing , Section 9.4, PHIF Pin Multiplexing , Section 8.2.3, Power
Management , and Section 7.7.1, SIO2 Features .
§ Indicates signal is internal and not necessarily observable at pins depending on how the JTAG is set up.