Lucent Technologies DSP1611, Information Manual, Page: 299 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
JTAG Test Access Port April 1998
11-14
DRAFT COPY
Lucent Technologies Inc.
11.3 Elements of the JTAG Test Logic
(continued)
11.3.4 The Boundary-Scan Register—JBSR (continued)
Boundary-Scan Bidirectional Cells: The B-type cells of the JBSR (see Figure 11-7 ) combine the I-type and
O-type cells into one. Every bidirectional cell is associated with a direction control cell (a DC-type cell). This is not
a one-to-one relationship, and, similar to 3-state outputs, a single DC cell can control several B cells. The combina-
tion of the B-cell and the corresponding DC cell fully controls the state of a bidirectional pin. The bidirectional cell
contains one shift-register stage. It can be reconfigured into an output cell or an input cell depending on the value
of the signal HOLI (high out, low in) obtained from the corresponding direction control cell. If HOLI equals one, the
output stage captures the device output signal (DO) and the bidirectional cell acts like an O cell. If HOLI equals
zero, the output stage captures the value of the input pin signal (PI) and the cell is configured as an I cell. The sig-
nal HOLI and its origin are further described in the description of the DC cell.
5-4133
Figure 11-7. Bidirectional Cell
The MODE signal, similar to the cells discussed before, determines whether the bidirectional pin is controlled by
the normal device logic or by the test logic. If MODE equals zero, the bidirectional pin's function is defined by the
device logic and the HOLI signal corresponds to the direction control signal from the device. In this case, the cell's
output to the pin (PO) is tied to the corresponding signal from the device (DO) and the cell's input from the pin (PI)
drives the device logic (DI). In the test mode (i.e., with MODE = 1), the bidirectional pin is under the control of the
boundary-scan register and HOLI corresponds to the value scanned into the DC cell. In this case, both the pin out-
put (PO) and the device logic input (DI) are tied to the scanned-in value of the update register.
Direction Control Cells: The DC-type cells of the JBSR (see Figure 11-8 ) are similar to the OE-type cells and are
used with the bidirectional cells discussed before. They consist of a shift-register cell with parallel load capability
from input (during capture-DR state) and parallel load capability into the output stage (during update-DR state).
The output stage is cleared when entering the test-logic-reset state that prevents bus contention upon the first
entry into the EXTEST instruction (as discussed before in the description of the OE cells). The signal HOLI selects
the source of captured data in the bidirectional cell. HOLI corresponds to the bidirectional enable signal from the
device logic (OEI) if MODE equals zero or to the scanned-in signal if MODE equals one. Note that the 3-state
buffer of the bidirectional pin is not driven by HOLI. Instead, it is driven by OE that is the same as HOLI except dur-
ing INTEST when it is a zero. This will put the biputs in the high-impedance state during internal tests and, thus,
prevent them from causing contention on external buses.
TO PIN
FROM PIN
SERIAL
IN
SERIAL
OUT
PO
PI
DO
DI
HOLI
FROM CHIP
FROM DC CELL
TO CHIP
SO