Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Hardware Architecture
Lucent Technologies Inc.
DRAFT COPY
2-17
2.2 Core Architecture Overview
(continued)
2.2.1 Data Arithmetic Unit (continued)
The multiplier executes a 16-bit by 16-bit multiply and stores the 32-bit product in the product register (p) in one
instruction cycle. Data for the multiplier's inputs comes from the 16-bit x register and the upper 16 bits (high half) of
the 32-bit y register.
For multiply/ALU instructions, the x register can be loaded with coefficients from X-memory space or data from Y-
memory space. The high half of the y register can be loaded from Y-memory space or the high or low half of an
accumulator. If the single-cycle square mode is set in the auc register, an instruction that loads the y register also
loads the x register with the same data. A multiply instruction then performs a squaring function.
x, y, yl, p, pl, a0, a0l, a1, and a1l are also included in the general set of registers used for data move instructions.
If the 32-bit registers are used in 16-bit instructions, the l suffix identifies the low half of the register and no suffix
identifies the upper half. For example, a0 means bits 31—16 of a0 and a0l means bits 15—0.
In addition to being used as an adder in the multiply/accumulate instructions, the 36-bit ALU provides the capability
to implement functions and algorithms in the DSP1611/17/18/27/28/29 device that conventionally are executed in a
microcomputer or a microprocessor. Operands to the ALU can be data in y, p, a0, or a1, or they can be immedi-
ates. The ALU sign-extends 32-bit operands from y or p to 36 bits, and it produces a 36-bit output (32 data bits
and 4 guard bits) in one instruction cycle. Either accumulator can receive the 36-bit result. The ALU supports
dyadic (two-operand) functions including addition, subtraction, and logical AND, OR, and XOR. It also supports
monadic (single-operand) functions including rounding, two's complement negation, incrementing, and left and
right shifts of 1, 4, 8, or 16 bits. More general shifting is available with the bit manipulation unit (see
Section 2.5, Bit
Manipulation Unit (BMU) ).
The auc (arithmetic unit control) register has five functions. It selects or deselects clearing of the lower 16-bit word
of the y register and accumulators when the upper word is written. It selects or deselects saturation on overflow for
the accumulators. It selects one of four alignments of data in the p register. It controls whether the pseudorandom
sequence generator is reset if the pi register is written (see
Section 5.1.6, DAU Pseudorandom Sequence Genera-
tor (PSG) ). It selects the single-cycle squaring mode (See Section 5.1.2, Multiplier Functions ). The auc register is
reset to all zeros at chip reset. The psw (processor status word) register contains flags from ALU operations and
provides access to the guard bits in the accumulators. The c<0—2> counters are 8 (signed) bits wide and can be
used to count events such as the number of times the program has executed a sequence of code. They are con-
trolled by the conditional instructions and provide a convenient method of program looping.
2.2.2 Y Space Address Arithmetic Unit (YAAU)
The YAAU supports high-speed, register-indirect data memory addressing with postmodification of the address
register. Four general-purpose 16-bit registers r<0—3> store read or write addresses for on-chip or off-chip RAM.
Two 16-bit registers rb and re allow zero-overhead modulo addressing of data for efficient filter implementations.
Two signed registers j and k are used to hold user-defined postincrements. Fixed increments of +1, –1, and +2 are
also available, but the +2 increment is only available with compound addressing. Four compound-addressing
modes are provided to make read/write operations more efficient.
The YAAU allows direct addressing of data memory. During direct addressing, the base register (ybase) stores the
11 most significant bits of the address. The direct address instruction contains 5 bits that are concatenated with
the 11 bits in ybase to form a complete 16-bit address. The instruction also specifies one register (DR) of 16 pos-
sible registers. A data move then takes place between the memory location specified by the 16-bit address and the
register selected by the DR field.
The YAAU decodes the 16-bit data memory address and provides individual enables for each 1 Kword bank of on-
chip dual-port RAM and three external data memory segments (ERAMHI, ERAMLO, and IO). One individual
address in the IO memory segment also has an individually decoded output DSEL
1
facilitating glueless memory-
mapped I/O.
1.Not available in the DSP1627/28/29.