Lucent Technologies DSP1611, Information Manual

Page: 388 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Instruction Set Summary April 1998
B-7
DRAFT COPY
Lucent Technologies Inc.
redo K
(loop in cache; cache contents unaffected)
Execute the current contents of the cache K times.
The current contents of the cache (loaded by a previous do instruction) are executed within the cache K additional
times. The iteration count K can be between 1 and 127 inclusive.
If K is equal to 0, the iteration count is taken from the value in the cloop register that must contain a value between
1 and 127 inclusive. The cloop register will be decremented to zero at the end of the redo instruction.
Notes on cache performance:
The redo instruction executes in two cycles. All instructions require the in-cache time to execute, except the last
instruction of the last iteration that requires the out-of-cache time to execute. Thereafter, instructions fetched
from X-space require their normal out-of-cache time to execute.
Bit 15 14 13 12 11 10 9 8 7 6—0
Field
0 1 1 1 0 0 0 0 0 K
Words: 1
Cycles: 2
Group: Cache
Addressing: Immediate
Flags affected: None
Interruptible: No
Cacheable: No
Format: 10