Lucent Technologies DSP1611, Information Manual, Page: 293 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
JTAG Test Access Port April 1998
11-8
DRAFT COPY
Lucent Technologies Inc.
11.3 Elements of the JTAG Test Logic
(continued)
11.3.4 The Boundary-Scan Register—JBSR
The JTAG boundary-scan register is a 106-bit scannable register containing a register cell for every digital I/O pin
as well as for every 3-state enable signal of the device. The four JTAG TAP pins, ground pins, and power pins are
excluded from the boundary-scan register as specified by the standard. All of the cells contain a parallel output
stage that is updated on the falling edge of TCK. New data will appear only in the update DR state under full con-
trol of the test bus controller. Consequently, hazardous conditions, such as reset of the device or contention on
external buses, can be prevented.
Table 11-2 defines the register cell types.
Tables 11-3 and 11-4 show the configuration of the boundary-scan register.
Table 11-2. Boundary-Scan Register Cell Type Definitions
Cell Type Meaning
I Input Cell.
O 3-state Output Cell.
B Bidirectional (I/O) Cell.
OE 3-state Controller Cell.
DC Bidirectional Controller Cell.