Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Software Architecture
Lucent Technologies Inc.
DRAFT COPY
3-7
3.1 Register View of the DSP1611/17/18/27/28/29
(continued)
3.1.4 Flags
For reference purposes, the definitions of the flags are included in Table 3-6 and Chapter 4 , Instruction Set .
Table 3-6. Flag Definitions
Test Meaning Test Meaning
pl Result is nonnegative (not LMI) (
≥
0). mi Result is negative (LMI) (< 0).
eq Result is equal to 0 (LEQ) (= 0). ne Result is not equal to 0 (not LEQ) (
≠
0).
gt Result is greater than 0 (not LMI and
not LEQ) (> 0). le Result is less than or equal to 0 (LMI or
LEQ) (
≤
0).
lvs Logical overflow set (LLV). lvc Logical overflow clear (not LLV).
mvs Mathematical overflow set (LMV). mvc Mathematical overflow clear (not LMV).
c0ge
†
† Testing each of these conditions increments the respective counter being tested.
Counter 0 greater than or equal to 0. c0lt
†
Counter 0 less than 0.
c1ge
†
Counter 1 greater than or equal to 0. c1lt
†
Counter 1 less than 0.
heads
‡
‡ The heads or tails condition is determined by a randomly set or a cleared bit. The bit is randomly set with probability of 0.5.
The random bit is generated by a 10-stage pseudorandom sequence generator (PSG) that is updated after either a heads or
tails test. (See
Section 5.1.6, DAU Pseudorandom Sequence Generator (PSG) for more details.)
Pseudorandom sequence bit set. tails
‡
Pseudorandom sequence bit clear.
true The condition is always satisfied in an
if instruction. false The condition is never satisfied in an if
instruction.
allt
§
§ These flags are only set after an appropriate write to the BIO port (cbit register).
All true—all BIO input bits tested com-
pared successfully. allf
§
All false—no BIO input bits tested com-
pared successfully.
somet
§
Some true—some BIO input bits
tested compared successfully. somef
§
Some false—some BIO input bits
tested did not compare successfully.
oddp Odd parity from BMU operation. evenp Even parity from BMU operation.
mns1 Minus 1 result of BMU operation. nmns1 Not minus 1 result of BMU operation.
npint Not PINT used by Hardware Develop-
ment System. njint Not JINT used by Hardware Develop-
ment System.
lock The PLL has achieved lock and is sta-
ble (DSP1627/28/29 only). ebusy ECCP busy indicates error correction
coprocessor activity (DSP1618/28
only).