Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Lucent Technologies Inc.
DRAFT COPY
3-1
3 Software Architecture
This chapter contains a variety of topics on the software and programming of the device. First, the registers and
their properties are listed in
Section 3.1, Register View of the DSP1611/17/18/27/28/29 . Next, the memory space
and addressing modes are described Section 3.2, Memory Space and Addressing . Then, the arithmetic and preci-
sion for calculations in the DAU are described in Section 3.3, Arithmetic and Precision . Section 3.4, Interrupts , dis-
cusses both the vectored interrupts and the DSP16A compatible interrupts. (The DSP16A compatible interrupts
are available on the DSP1617 only.)
Section 3.5, Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only) ,
describes the DSP1627/28/29’s phase-lock loop based clock synthesizer. And finally, the flexible power manage-
ment features are discussed in
Section 3.6, Power Management .
3.1 Register View of the DSP1611/17/18/27/28/29
3.1.1 Types of Registers
Registers are either accessible by the program or through the DSP1611/17/18/27/28/29 pins. Accessible by pro-
gram means they can be selected in data move instructions. The program-accessible registers are denoted by
lower-case names; the pin-accessible registers are denoted by upper-case names. The registers are generally of
three types:
Data—used for storing data that, in turn, become operands for the functional operators.
Control and status—used for setting different configurations of the machine (control) or indicating the configura-
tion of the machine (status).
Addressing—used for storing information that points to a memory location. In some cases, addressing registers
can be used as general-purpose data registers accessible by data move instructions.
A very important register not directly accessible to the programmer or through external pins is the PC (program
counter register). The machine automatically controls the PC to properly sequence the instructions.
Table 3-1 lists the general set of program-accessible registers sorted by function. Table 3-2 sorts them alphabeti-
cally and includes their type and location. Table 3-3 lists the pin-accessible registers. Figure 3-1 depicts the pro-
gram-accessible registers in a block diagram of the whole chip.
Table 3-1. Program-Accessible Registers by Function
Register Name Function
r0, r1, r2, r3, j, k, rb, re, ybase YAAU addressing
pt, pr, pi, i XAAU addressing
p, pl, x, y, yl, a0, a0l, a1, a1l, aa0, aa1 DAU data
auc, psw DAU control
c0, c1, c2 Counters
sdx, sdx2 SIO data
srta, srta2, tdms, tdms2, saddx, saddx2, sioc, sioc2 SIO control
pdx<0—7> (pdx0 only for DSP1611/18/27/28/29) PIO or PHIF data
phifc (DSP1611/18/27/28/29 only) PHIF control
pioc (DSP1617 only) PIO control
eir, ear, edr (DSP1618/28 only) ECCP instruction, address, and data registers
pllc (DSP1627/28/29 only) Control register for clock synthesizer
cbit, sbit BIO data and control
Note: Registers sioc, sioc2, srta, srta2, tdms, and tdms2 are not readable. Alternate accumulators aa0 and aa1 are only acces-
sible with the BMU swap instruction.